Array substrate and micro light-emitting diode display panel
A technology for light-emitting diodes and array substrates, which is used in identification devices, instruments, semiconductor devices, etc., can solve the problems of scratches and short circuits on the substrate, and scratches on the metal layer easily, and achieves the effect of preventing scratches and avoiding scratches and short circuits.
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Embodiment 1
[0037] see figure 1 , the embodiment of the present application provides an array substrate 10, the array substrate 10 includes a first area AA for arranging micro light emitting diodes and a second area BB surrounding the first area AA, the array substrate 10 includes: a base 11; The array functional layer on the substrate 11, the array functional layer includes welding terminals 164 arranged in an array, and the welding terminals 164 are used to electrically connect with the micro light emitting diodes; the protective layer 187 arranged on the array functional layer, the protective layer 187 includes the first sub- The protection layer 18 and the second sub-protection layer 17 , the second sub-protection layer 17 is disposed on the array function layer, and the first sub-protection layer 18 is disposed on the second sub-protection layer 17 . Wherein, the first sub-protective layer 18 is a metal oxide layer, the second sub-protective layer 17 is an inorganic material layer or...
Embodiment 2
[0055] see image 3 , the embodiment of the present application provides an array substrate 10, the array substrate 10 includes a first area AA for arranging micro light emitting diodes and a second area BB surrounding the first area AA, the array substrate 10 includes: a base 11; The array functional layer on the substrate 11, the array functional layer includes welding terminals 164 arranged in an array, and the welding terminals 164 are used to electrically connect with the micro light emitting diodes; the protective layer 187 arranged on the array functional layer, the protective layer 187 includes the first sub- The protection layer 18 and the second sub-protection layer 17 , the second sub-protection layer 17 is disposed on the array function layer, and the first sub-protection layer 18 is disposed on the second sub-protection layer 17 . Wherein, the first sub-protective layer 18 is a metal oxide layer, the second sub-protective layer 17 is an inorganic material layer or...
Embodiment 3
[0071] see Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , image 3 , illustrates a manufacturing process of the array substrate 10 in the second embodiment, but the array substrate 10 can also be manufactured using other processes or photomask sequences, which is not limited here.
[0072] Specifically, a manufacturing process of the array substrate 10 in Embodiment 2 includes: a first photomask, such as Figure 4 As shown, a first metal layer 12 is formed on a substrate 11, and the first metal layer 12 is patterned to include a gate 121 and a first electrode 122; the second photomask, such as Figure 5 As shown, a gate insulating layer 13 is formed on the first metal layer 12, an active layer 145 is formed on the gate insulating layer 13, the upper surface of the active layer 145 is doped, and the active layer 145 can be amorphous silicon or metal oxide, the active layer 145 includes a first sub-active layer 14 and a second sub-active layer 15, and a first ...
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Abstract
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