Neural network weight storage method, reading method and related equipment

A neural network and weight technology, which is applied in the computer field, can solve the problems of high chip power consumption and cost, optimal chip throughput, and difficult storage space, achieve low DDR transmission bandwidth, solve the problem of loop Effects of Cache Overflow, Power and Cost Reduction

Active Publication Date: 2021-11-26
AZURENGINE TECH ZHUHAI INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the above solutions still have various disadvantages, such as large transmission bandwidth, large storage space or difficulty in making the throughput of the chip reach an optimal state, resulting in high power consumption and cost of the chip

Method used

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  • Neural network weight storage method, reading method and related equipment
  • Neural network weight storage method, reading method and related equipment
  • Neural network weight storage method, reading method and related equipment

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Embodiment Construction

[0075] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiment of the application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the application. Obviously, the described embodiment is only It is an embodiment of a part of the application, but not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application.

[0076] The terms "comprising" and "having" and any variations thereof appearing in the specification, claims and drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally furth...

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Abstract

The present application provides a neural network weight storage method, reading method and related equipment, wherein the storage method includes: curing the weight of the first layer of the neural network in the static memory of the static random access memory when the system is initialized ; Obtain the cumulative length of the weights of each layer of the neural network in the circular cache of the static random access memory; solidify the weights of the target layer in each layer in the static memory according to the cumulative length of the weights; execute the next acquisition of the weights The operation of accumulating the length repeats the operation of obtaining the accumulative length of the weight for several times until there is no target layer in each layer; the size of the circular buffer is set according to the accumulative length of the corresponding weight when there is no target layer in each layer. The embodiments of the present application help to solve the problems of overflow and underflow of the circular buffer, so that the chip can achieve better throughput, and further reduce the power consumption and cost of the chip.

Description

technical field [0001] The present application relates to the field of computer technology, in particular to a neural network weight storage method, reading method and related equipment. Background technique [0002] As the computing power of AI (Artificial Intelligence, artificial intelligence) chips is getting stronger and the neural network model is getting deeper and deeper, the AI ​​processor needs to read a large amount of weight data for calculation when performing training or reasoning. In order to reduce the power consumption and cost of the chip, relevant personnel have done in-depth research on the storage of neural network weights. The current mainstream storage solutions include high-speed DDR (Double DataRate, double-rate synchronous dynamic random access memory) combined with Cache cache, or using super large capacity of SRAM (Static Random-Access Memory, static random access memory), and further there is a scheme using ping-pong cache. However, the above-men...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0895G06F12/0868G06F1/3234G06N3/063
CPCG06F12/0895G06F12/0868G06F1/3275G06N3/063G06F2212/1044G06F2212/1016G06F2212/221G06F2212/1028Y02D10/00
Inventor 雷宇李原朱建斌付尧永田敏雄
Owner AZURENGINE TECH ZHUHAI INC
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