Mainboard and time sequence control method and device

Abstract

The invention discloses a mainboard which comprises a clock source and a processor, at least two clock connectors are connected in series between the clock source and the processor, and the clock connectors are connected through a clock cable. The invention further discloses a time sequence control method, and the method comprises the steps: determining the signal transmission time difference under the condition that the data transmission direction is from the equipment card to the processor; and determining the total length of the clock cable according to the signal transmission time difference and the time sequence requirement so as to use the clock cable with the total length between the clock connectors to perform time sequence control. According to the mainboard, at least two clock connectors are connected in series between the clock source and the processor of the mainboard, the clock connectors are connected through the clock cable, the space on the mainboard is not occupied, time sequence control can be effectively carried out by adjusting the length of the clock cable, the signal quality can be optimized, and the link design risk is reduced. The invention further discloses a time sequence control device which has the corresponding technical effects.

Description

technical field [0001] The present application relates to the field of computer application technology, and in particular to a motherboard and sequence control method and device. Background technique [0002] In the PCIe (peripheral component interconnect express, high-speed serial computer expansion bus standard) link design process of the server system, the jitter control of the clock (Clock) signal line is particularly important. In the PCIe topology based on the common clock (Commom Clock) architecture, if the clock link of the sending chip and the clock link of the receiving chip are too different, it will affect the recognition of the PCIe signal of the receiving chip, which will easily lead to some unforeseen problems. , increasing system design risk. Therefore, there are certain control requirements for the jitter of the clock signal line in the server system. [0003] For the control requirements of clock signal line jitter, it is usually approximately converted i...

AI Technical Summary

Problems solved by technology

However, this method has certain limitations and cannot be applied in some special application scenarios

For example, with the increase of the wiring density on the printed circuit board, sometimes it is difficult to find enough space for wiring, or, in order to meet the required length, the wiring spacing must be compressed, which will bring crosstalk between signals and increase design risk

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