Fin field effect transistor source-drain parasitic resistance extraction method

Abstract

The invention discloses a fin field effect transistor source-drain parasitic resistance extraction method, which can avoid the problem of serious leakage current and improve the extraction accuracy of the source-drain parasitic resistance. The method comprises the following steps: decomposing the source-drain parasitic resistance into a plurality of decomposed parasitic resistances, dividing different test intervals according to the distribution condition of the decomposed parasitic resistances, measuring source-drain parasitic resistances of different test intervals based on the Kelvin test structure, measuring fin lengths of the different test intervals, and calculating and obtaining decomposition parasitic resistances based on the linear equation, the source-drain parasitic resistances of the different test intervals and the fin lengths.

Description

technical field [0001] The invention relates to the technical field of field effect transistors, in particular to a method for extracting source and drain parasitic resistances of fin field effect transistors. Background technique [0002] Fin Field Effect Transistor (FinFET) is a complementary metal-semiconductor transistor. The main difference between it and the planar MOSFET structure is that its channel is composed of raised fins on the insulating substrate, and the source and drain are distributed at both ends. The gate is close to its side wall and top for auxiliary current control. The fin structure increases the surface of the gate around the channel and strengthens the control of the gate on the channel, which can effectively alleviate the short channel in planar devices. effect, greatly improving circuit control and reducing leakage current, and at the same time can greatly shorten the gate length of transistors. [0003] As CMOS technology enters the 16nm and 14n...

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Problems solved by technology

There have been related studies in the existing literature, but most of them use modeling and simulation methods to simulate the variation of the process and the electrical characteristics of components. The source-drain parasitic resistance needs to be extracted during the simulation, but the source-drain parasitic resistance of the FinFET in the prior art Extraction is more difficult, there are few ways to achieve separate extraction of parasitic resistance, and there are problems such as low extraction accuracy of source and drain parasitic resistance

For example, a conventional test structure for source and drain parasitic resistance of field effect transistors is provided in the prior art, which measures and obtains different source and drain parasitic resistances by changing the distance between two adjacent gate regions, but as the two adjacent With the increase of the distance between the gate regions, the length of the fin between the two gate regions increases, and the leakage current also increases, which seriously affects the extraction accuracy of the source-drain parasitic resistance.

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