Incremental segmentation processing method, device, computer equipment and storage medium

Abstract

The invention provides an incremental segmentation processing method, device, computer equipment and storage medium, belonging to the field of segmentation algorithms. The specific method includes acquiring and parsing an initial syntax tree structure of an initial design file and a modified syntax tree structure of modifying the design file; Run the initial operation data of the initial design file in the whole process to set the first programmable logic device; compare the initial syntax tree structure and modify the difference nodes between the syntax tree structures; identify the first programmable logic device and the first programmable logic device according to the difference nodes Two programmable logic devices; the optimal allocation between the node and the second programmable logic device under the node position distribution state is obtained by calculation, and the incremental division processing result is obtained. Through the processing solution of the present application, a design file with a small amount of modification can be quickly divided and processed, thereby saving time and improving efficiency.

Description

technical field [0001] The present invention relates to the field of segmentation algorithms, in particular to an incremental segmentation processing method, device, computer equipment and storage medium. Background technique [0002] Before officially putting into the factory for chip production, it is necessary to verify the correctness and performance indicators of the RTL language design or netlist logic in the chip design file. In chip design, the programmable logic verification array is often used to verify the RTL design written in Verilog / SystemVerilog / VHDL and other languages. It is necessary to generate a syntax tree inside the computer, and spread (flatten) the boundary nodes of the division boundary in the syntax tree to the top layer. After being abstracted into a hypergraph, the segmentation algorithm engine divides the nodes into a specified number of different parts on the hypergraph, and each part is restored to an RTL-level design through the process of con...

AI Technical Summary

Problems solved by technology

Among them, the logic synthesis process will consume a lot of time. In general, a large-scale design will take dozens of hours, and the layout and routing of each part of the netlist obtained from the synthesis will also take dozens of hours.

[0003] However, in the logic verification process, sometimes it is necessary to make a small amount of modification to the design to realize the debugging of the design file, so as to debug errors or optimize performance. This kind of debugging operation is inevitable and occurs frequently.

But even if the user only changes a limited number of operators for debugging, which may be a small change of one thousandth or one ten thousandth of the entire design, the entire process of RTL segmentation will have to be repeated, and dozens of times will need to be repeated. The consumption of hours not only wastes a lot of time and computing resources, but also the debugging efficiency is extremely low, and may even affect the production plan of the entire product

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