Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel. The array substrate comprises a plurality of scanning lines, a plurality of data lines, a plurality of data lines without black matrixes and a plurality of sub-pixels, wherein the data lines are located above the data lines, and the sub-pixels are defined by the scanning lines and the data lines in a crossed mode. Each sub-pixel is divided into a main pixel area and an auxiliary pixel area, a scanning line is arranged corresponding to each row of sub-pixels, and the scanning lines are located between the main pixel areas and the auxiliary pixel areas; the main pixel area comprises a first thin film transistor, a main area storage capacitor and a main area liquid crystal capacitor, and the auxiliary pixel area comprises a second thin film transistor, a third thin film transistor, an auxiliary area storage capacitor and an auxiliary area liquid crystal capacitor; wherein the drain electrode of the third thin film transistor is connected with the data line of the non-black matrix, so that the pixel aperture opening ratio is increased, meanwhile, a preset electrode is omitted, and the occurrence probability of poor pixels can be effectively reduced.

Description

technical field [0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background technique [0002] In the 3T pixel unit structure, the pixel unit is divided into a main pixel area (Main Pixel) and a sub-pixel area (SubPixel). In the prior art, the problem of viewing angle is improved through the different degrees of liquid crystal inversion in the main pixel area and the sub-pixel area. [0003] The main pixel area is driven by a first thin film transistor (Thin Film Transistor, TFT), and the sub-pixel area is jointly driven by a second thin film transistor and a third thin film transistor for pulling down the voltage of the sub-pixel area. Wherein, the gate of the first thin film transistor in the main pixel area is connected to the corresponding scanning line Gate, the source of the first thin film transistor is connected to the corresponding data line Data, and the drain of the first thin f...

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Problems solved by technology

[0004] However, this pixel design is connected to the preset electrode (sharebar) electrode through the drain of the third thin film transistor. The preset electrode is located under the pixel electrode (ITO) trunk. Poor alignment between the preset electrode and the pixel electrode will reduce the pixel transmittance. , at the same time, foreign matter between the default electrode and the underlying common electrode metal may cause poor light lines, resulting in a decline in production yield

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