32results about How to "Improve the stability of electrical properties" patented technology

The invention provides a fabrication method of a low-temperature polycrystalline silicon thin-film transistor (TFT) substrate structure and the low-temperature polycrystalline silicon TFT substrate structure. According to the fabrication method of the low-temperature polycrystalline silicon TFT substrate structure provided by the invention, patterns, which are consistent in law and size, of heat-conducting insulating layers are arranged below a buffer layer of a drive TFT region; the heat-conducting insulating layers absorb heat in the subsequent excimer laser annealing treatment process, so that the cooling speed of amorphous silicon is quickened to form crystal nucleus; the crystal nucleus gradually grows in the annealing process; the heat-conducting insulating layers have the patterns which are consistent in law and size, so that polycrystalline silicon grains formed by the drive TFT region have relatively good consistency; the grains are relatively large; and the electrical consistency of a drive TFT is ensured. According to the low-temperature polycrystalline silicon TFT substrate structure provided by the invention, the patterns, which are consistent in law and size, of the heat-conducting insulating layers are arranged below the buffer layer of the drive TFT region; the polycrystalline silicon grains of the drive TFT region are relatively good in consistency and relatively large; and the electrical consistency of the drive TFT is relatively good.

Provided are a mercury-free silver oxide button cell and a preparation method thereof. A preparation method of zinc gel of the cell comprises the steps that 1, an electrolyte is prepared, wherein potassium hydroxide and zinc oxide are added into water by mass, and the electrolyte is obtained after potassium hydroxide and zinc oxide are completely dissolved; 2, lead-free mercury-free zinc powder, polyacrylic acid, polyacrylate, indium hydroxide and indium oxide are put into a stirring tank of a zinc mixer by mass and stirred and mixed to be uniform, the zinc powder mixture is obtained, the electrolyte is added into the stirring tank slowly, the materials are stirred to be uniform, vacuumizing is conducted, and the zinc gel of the mercury-free silver oxide button cell is obtained. Compared with the prior art, the zinc gel of the mercury-free silver oxide button cell is formed by mixing and vacuum stirring the zinc powder mixture and the electrolyte, the formula of the raw materials is reasonable, the expansion rate of the obtained zinc gel is small, and the storing time of the prepared mercury-free silver oxide button cell is long.

The invention relates to a conductive carbon paste for a flexible pressure sensor, a preparation method thereof, and a pressure sensor. In terms of mass percentage, the raw material formula of the conductive carbon paste includes the following components: 1-25% of graphene, 0.04% of carbon nanotube ~1.5%, dispersant 0.001~1%, oleoresin 5~45%, thickener 1~10%, coupling agent 0.01~5%, first solvent 25~70% and second solvent 20~40%. The conductive carbon paste of the present invention adds graphene sheets and a small amount of carbon nanotubes to the resin system, and cooperates with the use of dispersants, coupling agents and plasticizers, so that the prepared conductive carbon paste has high sensitivity and high stability , low minimum detection limit, bending resistance, strong adhesion with flexible substrates, etc. Under the action of pressure, the conductive network formed by graphene and carbon nanotubes in the cured conductive carbon paste resin system changes, and the cured conductive carbon paste has increased resistance, high pressure sensitivity, and small pressure changes can be sensed.

The invention discloses an organic thin film transistor, comprising a substrate, a source / drain layer, a first buffer layer, a semiconductor layer, a gate insulating layer, and a gate electrode, wherein the source / drain layer is located on the substrate and has a source region and a drain region; the first buffer layer is located between the source region and the drain region and covers at least part of the source region and at least part of the drain region; the semiconductor layer is located on the source / drain layer and the first buffer layer; the first buffer layer is located among the semiconductor layer, the source region, the drain region, and the substrate; the gate insulating layer covers the source / drain layer and the semiconductor layer; the gate electrode is located on the gateinsulating layer, and part of the gate insulating layer is located between the gate electrode and the semiconductor layer; and the first buffer layer may be used to fill the space between the sourceregion and the drain region to prevent the semiconductor layer from being formed on the wedge undercut structure of the source region and the drain region, so that the semiconductor layer has an eventhickness to improve the electrical stability of the organic thin film transistor.

The present invention provides an array substrate and a display panel, wherein the array substrate includes: a plurality of scanning lines and a plurality of data lines respectively intersecting the plurality of scanning lines to define a plurality of pixel units; each pixel unit It includes a master pixel area and a slave pixel area, and the slave pixel unit includes a slave pixel electrode; a plurality of DBS electrode lines are arranged above the plurality of data lines; For the shared thin film transistor, the gate of the shared thin film transistor is connected to the corresponding scanning line, the source of the shared thin film transistor is connected to the slave pixel electrode, and the drain of the shared thin film transistor is connected to the corresponding DBS electrode line. The present invention removes the deep hole connection between the source or drain of the shared thin film transistor and the A-com common electrode in the prior art, increases the area of ​​the display area of ​​the product, increases the aperture ratio, and thus improves the electrical properties of the 3T structure design stability.

The present application discloses a method for preparing a sample, the method comprising: providing a semiconductor structure, the semiconductor structure including a stack structure, a channel structure penetrating the stack structure, and a channel contact on the channel structure; The stacked structure includes alternately stacked gate layers and dielectric layers; a first sample preparation process is performed on the semiconductor structure to form a cross section that exposes the stacked structure and a part of the channel contact; removed by an etching solution the gate layer and the exposed part of the channel contacts in the semiconductor structure, leaving the unexposed channel contacts; and performing a second sample preparation process on the semiconductor structure, so that the processed A sample includes the channel structure and the channel contact on the channel structure.

The embodiment of the invention discloses an array substrate and a manufacturing method of the array substrate. The array substrate comprises a substrate, a buffer layer, a semiconductor layer, an insulating layer and a grid layer. The buffer layer is arranged on the substrate; the semiconductor layer is arranged on the buffer layer; the insulating layer covers the buffer layer and the semiconductor layer; the grid electrode layer is arranged on the insulating layer; the semiconductor layer comprises a current carrier channel; the carrier channel is located on one side, facing the insulating layer, of the semiconductor layer; the insulating layer comprises a first thin film layer and a second thin film layer; the first thin film layer covers the semiconductor layer and the buffer layer; the second thin film layer covers the first thin film layer; the grid electrode layer is located on the second thin film layer; the density of the first thin film layer is larger than that of the secondthin film layer; and the carrier channel is connected with the first thin film layer. According to the scheme, the electrical stability of the array substrate can be improved.