Method for improving gap filling capability

Abstract

The invention relates to a method for improving a gap filling capability. The method comprises the following steps: step one, carrying out etching to form a spacer region having a certain depth-to-width ratio; step two, carrying out secondary etching on the spacer region; and step three, carrying out corresponding filling on the spacer region according to the requirement of the method. According to the method, primary and secondary etching or acid pickling processes are added based on the traditional method; the depth-to-width ratio of the spacer region is reduced; and the gap filling capability during the chip manufacturing is enhanced. The possibility of hole occurrence during the filling process is reduced with the enhancement of the gap filling capability, so that the possibility of occurrence of problems of short circuit and the like due to the hole existence is also reduced; and hence, the electrical stability of the chip is enhanced, thereby improving the yield of the finished chip and the economic benefits.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor devices, in particular to a method for improving gap filling capability. Background technique [0002] In the semiconductor method, the component size of the integrated circuit is required to be smaller and smaller, so that more components can be accommodated on a semiconductor chip. As the circuit edge becomes smaller and faster, the distance between the components is also getting smaller and smaller. Based on the special requirements of electrical breakdown, a wider spacer is required as a barrier layer. However, due to the small line width characteristics of the semiconductor method, the width of the barrier layer will make the spacing between Poly narrower, and Its depth will not change because of these, which leads to a large depth-to-width ratio between Polys, resulting in a reduction in the subsequent filling capacity. In the subsequent filling, pores are easy to be generated, and...

AI Technical Summary

Problems solved by technology

[0002] In the semiconductor method, the component size of the integrated circuit is required to be smaller and smaller, so that more components can be accommodated on a semiconductor chip. As the circuit edge becomes smaller and faster, the distance between the components is also getting smaller and smaller. Based on the special requirements of electrical breakdown, a wider spacer is required as a barrier layer. However, due to the small line width characteristics of the semiconductor method, the width of the barrier layer will make the spacing between Poly narrower, and Its depth will not change because of these, which leads to a large depth-to-width ratio between Polys, resulting in a reduction in the subsequent filling capacity. In the subsequent filling, pores are easy to be generated, and the existence of these pores will directly affect the follow-up. CONT filling, the pores generated during the filling will diffuse when the CONT is filled, which will cause a short circuit between the CONTs, causing the device to fail to work

[0003] In traditional methods, such as Figure 1a , 1b, 1c, 1d, the width of the spacer 1 is fixed after the etch dwell time, although some implant layer (implant layer) acid baths will be passed later, but these photoresist removal steps have no effect on the etching of the oxide layer. The rate is low, and basically has no effect on the width of the spacer. The spacer produced in this way has a large aspect ratio (such as Figure 1a shown), which will cause a reduction in the subsequent filling capacity (for example: ILD filling), and will form pores between fillers (for example: ILD) (such as Figure 1b shown)

The existence of void (void) 3 will form a conduction channel in the circuit, and in the subsequent CONT tungsten filling process, metal tungsten will be filled into the channel connected by the void (such as Figure 1d shown), resulting in a short circuit of the circuit, causing fatal damage to the device

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