Semiconductor structure, preparation method and application thereof

A semiconductor and metal structure technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of poor electrical stability and reliability of semiconductor devices, high contact resistance, etc.

Pending Publication Date: 2020-03-31
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a semiconductor structure, a method for preparing the semiconductor structure and its use, which are used to solve the problem of the electrical performance of the semiconductor device caused by the large contact resistance of the metal interconnection structure in the prior art. Problems with poor stability and reliability

Method used

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  • Semiconductor structure, preparation method and application thereof
  • Semiconductor structure, preparation method and application thereof
  • Semiconductor structure, preparation method and application thereof

Examples

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preparation example Construction

[0119] figure 1 It is a flowchart of the semiconductor structure preparation method of the present invention, and the preparation method includes the following steps:

[0120] Execute step S10, such as Figure 2a As shown, a substrate 1 is provided, and at least one first metal structure 11 is embedded in the substrate 1; the top surface of the first metal structure 11 is in the same plane as the top surface of the substrate 1. For example, the substrate 1 may be a general semiconductor structure after completing the front-end process (Front End Of Line, FEOL), and the first metal structure 11 includes electrical connection terminals (for example, transistors) for electrical connection with the outside. gate terminal of a device) or a contact formed on an electrical connection terminal (for example, a contact formed on a source / drain terminal of a transistor device).

[0121] In one embodiment, as image 3 As shown, the substrate 1 also includes a third stop layer 12 and an...

Embodiment approach

[0138] In the first embodiment, it is necessary to etch and open the first stop layer 2 first. During the process of etching the first stop layer 2, this may cause damage and deformation of the interlayer dielectric layer 3 exposed by the trench, affecting Subsequent filling of the second metal structure further affects the electrical stability and reliability of the finally formed device.

[0139] For this reason, the present invention discloses another kind of embodiment, comprises the following steps: first, as Figure 2b As shown in / 2g, the first groove A / groove B is used as a groove for forming a diffusion barrier layer 5, and a diffusion barrier material 50 is formed on the inner wall of the groove A / groove B; secondly, remove the material 50 located in the groove The diffusion barrier layer material 50 at the bottom of A / trench B, so as to form the diffusion barrier layer 5 on the sidewall of the trench A / trench B, and expose the first stop layer 2; finally , removing...

Embodiment 1

[0162] Such as Figure 2a-2b , as shown in 4a-4d, this embodiment provides a method for preparing a semiconductor structure, which specifically includes the following steps.

[0163] First, if Figure 2a As shown, a substrate 1 is provided, the substrate 1 includes a bottom dielectric layer 13 and a first metal structure 11, the first metal structure 11 is embedded in the bottom dielectric layer 13, and the first metal The top surface of the structure 11 is in the same plane as the top surface of the bottom dielectric layer 13; a first stop layer 2, an interlayer dielectric layer 3, and a second stop layer are sequentially formed on the substrate 1 from bottom to top 4. A third photoresist layer 91; as an example, the thickness of the first stop layer 2 is between 40-70nm, the thickness of the interlayer dielectric layer 3 is between 250nm-300nm, and the second stop layer The thickness of the layer 4 is 200%~250% of the thickness of the first stop layer 2, which is to preven...

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Abstract

The invention provides a semiconductor structure, and a preparation method and application thereof, and the preparation method comprises the steps: providing a substrate, wherein at least one first metal structure is embedded in the substrate; the top surface of the first metal structure and the top surface of the substrate are located on the same plane; forming an interlayer dielectric layer on the substrate; forming at least one groove in the interlayer dielectric layer, wherein the groove is exposed out of the top surface of the first metal structure; forming a diffusion barrier layer on the side wall of the trench; and forming a second metal structure in the trench on which the diffusion barrier layer is formed, wherein the second metal structure is directly bonded with the first metalstructure to realize electrical connection. According to the invention, by removing the diffusion barrier layer at the bottom, the interconnection contact resistance is reduced, RC delay is reduced,the dielectric layer between the layers can be protected, the through hole filling quality is improved, and in addition, an insulating material can be used as the diffusion barrier layer, so that theelectrical performance stability and reliability of the device are improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure, a method for preparing the semiconductor structure and an application thereof. Background technique [0002] In semiconductor manufacturing, with the development trend of VLSI, the feature size of integrated circuits is getting smaller and smaller, and interconnect resistance has become one of the important factors affecting the electrical performance and reliability of semiconductor devices. The resistance capacitor (RC) delay of the back-end interconnection tends to increase significantly, which affects the performance of the semiconductor device. In order to reduce the RC delay, on the one hand, the metal wire is developed from the original metal aluminum interconnection to the metal copper interconnection to reduce the resistance R of the wire; on the other hand, the interlayer dielectric material uses a Low-k material with a lower dielect...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/522H01L23/528H01L21/768
CPCH01L21/76807H01L21/76829H01L21/76832H01L23/5226H01L23/5283
Inventor 吴公一徐朋辉陈龙阳
Owner CHANGXIN MEMORY TECH INC
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