Field-programmable gate array device and memory power supply control method

Abstract

The embodiment of the invention discloses a field-programmable gate array device and a memory power supply control method therein, in the field-programmable gate array device, a power-off signal port and a sleep signal port are additionally arranged on a memory so that can flexibly switch among a low-power-consumption state, a high-power-consumption state, a full-enabling state and a full-power-off state according to a power-off signal and a sleep signal. The memory does not need to work in a full-enabling state all the time so that the power consumption of the memory in the field programmable gate array device is greatly reduced. Therefore, the problems that the working temperature of the field programmable gate array device is too high and heat dissipation is difficult are solved.

Description

technical field [0001] The present application relates to the field of digital circuits, in particular to a field programmable gate array device and a memory power control method. Background technique [0002] Field Programmable Gate Array (Field Programmable Gate Array, FPGA) device belongs to a semi-custom circuit in ASIC, it is a programmable logic array, which can effectively solve the problem that the number of original device gates is small . [0003] The utilization rate of the memory in the FPGA chip is low, for example, the utilization rate of the memory in the FPGA chip is 50%, and the remaining 50% of memory resources are not utilized, but these useless memory resources are still consuming power. In addition, even the utilized memory resource is not always in read and write state. In many cases, the memory is only in the read and write state for a small amount of time, and most of the time only needs to save the content. [0004] However, during the configurati...

AI Technical Summary

Problems solved by technology

[0004] However, in the configuration of the existing FPGA chip, all the functional logic of the memory will be powered on and enabled at one time, which causes a waste of power consumption of the FPGA chip

When applied on a large scale, the large power consumption will also lead to problems such as high temperature and difficulty in heat dissipation

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