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Fault-tolerant method of torus network based on topology reconfiguration and path planning

A technology of topology reconfiguration and path planning, applied in the direction of advanced technology, climate sustainability, sustainable communication technology, etc., can solve the problem of rising solution time, reduce delay, shorten rescheduling time, and facilitate load balancing Effect

Active Publication Date: 2022-05-31
BEIHANG UNIV +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Most of the existing TT message scheduling tables are generated based on Satisfiability Modulo Theories, and the configured constraints are input into the SMT solver to obtain the results. On the one hand, when the topology scale is large, the solution time is exponential On the other hand, if a node or link fails, it is necessary to change the constraints and re-solve, which is not suitable for online reconfiguration. A time-triggered network-on-chip (TTNoC) fault-tolerant method that supports online reconfiguration is still needed

Method used

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  • Fault-tolerant method of torus network based on topology reconfiguration and path planning
  • Fault-tolerant method of torus network based on topology reconfiguration and path planning
  • Fault-tolerant method of torus network based on topology reconfiguration and path planning

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Experimental program
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Effect test

Embodiment 1

[0204] The first TT message is marked as Msg

[0205] tt.src represents the source node, tt.dest represents the destination node, tt.length represents the message frame length, tt.period

[0216]

[0221] The avionics network-on-chip was configured according to Torus to obtain the avionics-on-chip topology. network on chip

[0228] Step 2: Set the area block-processing unit and the area block-router in each node-area block to obtain

[0229] respectively set one area block-processing unit and one area in the 6 area blocks obtained in step 1

[0230] For example, by the node NE

[0231] The same can be obtained: in the second area block QU

[0238] In the present invention, a built-in self-test mechanism is used to obtain fault information. The fault information BD includes node fault information

Embodiment 2

[0250] tt.src represents source node, tt.dest represents destination node, tt.length represents message frame length, tt.period

[0261]

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Abstract

The invention discloses a Torus network fault-tolerant method based on topology reconfiguration and path planning to solve the rescheduling problem of TT messages in an avionics system when the Torus network fails. On the one hand, this method improves the Torus structure to support topology reconfiguration; it adds a processing unit DPE and a router DR to each node-area block of the improved Torus network structure; on the other hand, the node busyness is used as a TT message to be scheduled Obtain the basis of the shortest path and the alternative path, and then search for the earliest continuous idle time length that can accommodate the current TT message transmission according to the shortest path. The method combines the static redundancy and dynamic reconstruction of the topological structure of the on-chip system, improves the reliability of the Torus network, and thus shortens the rescheduling time of the TT message when a fault occurs.

Description

Torus Network Fault Tolerance Method Based on Topology Reconfiguration and Path Planning technical field The present invention relates to the fault-tolerant method of avionics on-chip network, more particularly, refers to a kind of based on topology reconstruction A fault-tolerant method for Torus networks and path planning. The invention is aimed at the avionics on-chip network, and its network structure adopts The Torus network configuration. Background technique With the distributed integrated modular avionics system (Distributed Integrated Modular The proposal of the Avionics, DIMA) system and the development of integrated circuit technology, the future avionics system will move towards the realization of the chip. The current direction of the development of micro and small smart components. Among them, cross-domain micro and small intelligent components (such as sensors, microcontrollers, digital The interconnection network of signal processing units, etc.) ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L41/0677H04L45/12H04L45/02
CPCH04L41/0677H04L45/12H04L45/02Y02D30/50
Inventor 徐亚军李国梁阎冬李峭
Owner BEIHANG UNIV
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