RISC-V instruction processing method, storage medium and electronic equipment

Abstract

The invention relates to the technical field of RISC-V register architecture, and discloses an RISC-V instruction processing method, a storage medium and electronic equipment. The method comprises the steps: obtaining a specified RISC-V instruction, wherein the specified RISC-V instruction comprises an operation code field and a register field, the register field is used for storing a non-addressing code but not storing an addressing code, the non-addressing code points to a corresponding non-addressing register, and the addressing code points to a corresponding addressing register; and operating the non-addressing register according to the operation code of the operation code field. As the addressing code of the addressing register does not participate in the coding of the specified RISC-V instruction, the embodiment of the invention can save the digits for expressing the addressing code, that is, more instruction coding space is vacated, and the saved digits are beneficial to expressing more specified RISC-V instructions, thereby improving the code density.

Description

technical field [0001] The invention relates to the technical field of RISC-V register architecture, in particular to a RISC-V instruction processing method, storage medium and electronic equipment. Background technique [0002] The RISC-V architecture adheres to a simple design philosophy. There are only more than 40 RISC-V basic instruction sets, plus dozens of other modular extension instructions. Enterprises can use the RISC-V instruction set without paying licensing fees. [0003] In the RISC-V architecture, the registers of the processor are divided into two main categories: the first category is general-purpose registers, which are used to participate in various computing operations. The second type is addressing registers, which are used to participate in addressing. Usually, addressing registers are only used in situations associated with addressing, and addressing registers are not required to specify RISC-V instructions. [0004] However, in the prior art, when ...

AI Technical Summary

Problems solved by technology

Since the addressing register participates in the encoding of the specified RISC-V instruction, it will occupy a corresponding number of instruction bits, resulting in the inability to express more RISC-V instructions, thus wasting the instruction encoding space

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