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Planarization method

A planarization method and wafer technology, applied in the field of planarization, can solve problems affecting the yield rate of semiconductor devices, TSV contact failure, etc., and achieve the effects of reducing the yield rate of finished products, reducing labor load, and simple process

Pending Publication Date: 2021-10-01
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In the subsequent process, affected by temperature and stress, copper will be squeezed to form copper bumps on the top surface of TSV, which will not only cause TSV contact failure, but also affect the yield of semiconductor devices

Method used

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Embodiment Construction

[0034] Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.

[0035] In the following description of various exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of example different exemplary structures in which aspects of the disclosure may be implemented. It is to be understood that other specific arrangements of components, structures, exemplary devices, systems and steps may be utiliz...

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Abstract

The invention provides a planarization method, which comprises the following steps of providing a wafer with a silicon through hole, and filling metal copper in the silicon through hole, performing first heat treatment on the wafer to form first copper bulges, removing the first copper bulges, performing second heat treatment on the wafer from which the first copper bulges are removed to form second copper bulges, removing the second copper bulges, and carrying out third heat treatment on the wafer from which the second copper bulge is removed, and forming a dielectric layer on the surface of the wafer. According to the planarization method, the risk that the yield of finished products is reduced due to the fact that copper protrusions appear in the follow-up process is reduced, effective planarization of the TSV is achieved, the planarization method is simple in process, and the labor amount and the manufacturing cost are reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a planarization method. Background technique [0002] Through Silicon Via (TSV) is the core technology of interlayer vertical interconnection, and planarization after TSV electroplating and filling is a key step in manufacturing TSV. [0003] After the TSV is electroplated and filled with copper, the filled copper is annealed. As the temperature rises, grain boundary dislocation defects are easily generated inside the filled copper, thereby increasing the internal stress. In the subsequent process, affected by temperature and stress, copper will be squeezed to form a copper bump on the top surface of the TSV, which will not only cause TSV contact failure, but also affect the yield of the semiconductor device. [0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and ther...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768
CPCH01L21/76864H01L21/7684
Inventor 严勋徐亚超
Owner CHANGXIN MEMORY TECH INC