A manufacturing method of a three-dimensional memory device and its device structure
A technology of three-dimensional storage and manufacturing method, which is applied in the direction of semiconductor devices, electrical solid devices, electrical components, etc., can solve problems affecting product yield, and achieve the effect of improving process stability and yield
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Embodiment 1
[0037] refer to Figure 4-12 As shown, Embodiment 1 of the present invention proposes a method for manufacturing a three-dimensional memory device, including the following steps:
[0038] Such as Figure 4 As shown, a substrate 11 is provided, on which a three-dimensional storage device area 12 and a peripheral circuit area 13 located around the three-dimensional storage device area are respectively formed, and the three-dimensional storage device area includes sequentially formed on the substrate a multi-layer memory stack structure, the stack structure forms a stepped structure on at least one side thereof, and the height of the stack structure is higher than the height of the peripheral circuit area;
[0039] Such as Figure 4 and 6 As shown, a first buffer layer 14, a dielectric layer 15 and a barrier layer 16 are sequentially formed on the substrate 11 to cover the three-dimensional memory device region 12 and the peripheral circuit region 13, and the first buffer laye...
Embodiment 2
[0047] In this embodiment, the parts different from the above embodiments will be described, and the same parts will not be repeated.
[0048] The height difference between the stacked structure of the three-dimensional memory device and the peripheral circuit area is 3 microns to 6 microns. The number of layers of the stacked structure of the three-dimensional memory device is greater than or equal to 48 layers.
[0049] Preferably, the number of layers of the stacked structure of the three-dimensional memory device is 48 layers, 64 layers, 80 layers, 96 layers, 112 layers or 128 layers.
Embodiment 3
[0051] In this embodiment, the parts different from the above embodiments will be described, and the same parts will not be repeated.
[0052] Such as Figure 6 As shown, the first buffer layer 14 is a silicon dioxide layer prepared by a high density plasma (HDP) process. The thickness of the first buffer layer 14 is, for example, 100 angstroms to 1000 angstroms.
[0053] The dielectric layer 15 is a silicon dioxide layer prepared by a chemical vapor deposition process using orthoethyl silicate (TEOS) as a raw material. Its chemical reaction formula is as follows: Si(OC 2 h 5 ) 4 → SiO 2 +4C 2 h 4 +2H 2 O. The thickness of the dielectric layer 15 varies according to the height difference between the three-dimensional memory device region 12 and the peripheral circuit region 13, the purpose of which is to fill up the three-dimensional memory device region 12 and the peripheral circuit region 13 through the deposition of the dielectric layer 15. In the uneven area form...
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