High-speed low-power-consumption double-tail current dynamic comparator circuit

Abstract

The invention discloses a high-speed low-power-consumption double-tail current dynamic comparator circuit, which comprises a BUFFER circuit composed of two phase inverters and a comparator circuit composed of a pre-amplification circuit and a latch structure, a clock signal CLK1 is input from the input end, and a clock signal CLK2 slightly delayed relative to the CLK1 can be obtained at the output end of the BUFFER circuit; by controlling the on-off of NMOS transistors M1 and M2 in the pre-amplification circuit, the NMOS transistors M1 and M2 have the functions of receiving input signals and blocking a static current path; and in the latching stage, latching output ends OUT + and OUT-are latched in corresponding states through a latching structure, so that a quick latching function is realized. The circuit uses a structure similar to an inverter to control a signal transmitted to the input end of the pre-amplifier, so as to control the on-off of a static current path, and reduce the power consumption in the latching stage.

Description

Technical field [0001] The present invention relates to the field of integrated circuit design, and more particularly to a high-speed low-power dual-tail current dynamic comparator circuit. Background technique [0002] With the advancement of science and technology and the development of electronic communication industries, signal processing technology has been widely used, which greatly promotes innovation and progress in various industries, convenient and optimized human life. The comparator is an important component of the data converter, its delay, power consumption, and disorders directly affect the performance indicators of signal and data processing, industrial and companies in order to pursue performance and benefits, high-speed low power consumption has become an important development of electronic products. direction. Compared with the traditional dynamic comparator, the double-tail current dynamic comparator has two tail currents, all the way for input portions, provi...

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Problems solved by technology

[0004] There is a serious shortcoming in this circuit structure: assuming that IN+ is greater than IN-, in the latch stage, after the output of the comparator, M9 has been turned off, but M8, M2, M1, M5 and M10 are all in the conduction state, forming A quiescent current path, thus generating a large power consumption, which affects the performance of the dual-tail current dynamic comparator circuit

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