Partition filling unit and multi-voltage-domain low-power-consumption chip

Abstract

The invention discloses a partition filling unit and a multi-voltage-domain low-power-consumption chip, and the partition filling unit comprises a substrate layer, a polycrystalline silicon layer, a diffusion layer and a metal layer which are sequentially stacked. The diffusion layer comprises an N + diffusion layer and a P + diffusion layer, the substrate layer is partitioned into a first substrate and a second substrate, and when the partition filling units are arranged on the left side and the right side of the isolation unit, the substrates of the isolation unit are isolated. By implementing the embodiment of the invention, the setting flexibility of the isolation unit can be improved.

Description

technical field [0001] The technical field of chip design of the present invention, in particular, relates to a partition filling unit and a multi-voltage domain low-power chip. Background technique [0002] With the increasing integration of chips, more and more functions, and the practical needs of the mobile market, low-power chip design is becoming more and more respected. Under different application scenarios of the product, if some scenarios are not frequently used, it is desirable to turn off the power supply of these scenarios to save power; some scenarios need to work under high voltage; some scenarios need to work under low voltage. This is mapped to the chip, which is equivalent to that some modules that do not need to work often will be powered off to reduce power consumption; some high-performance, high-frequency modules need to provide high voltage; some low-performance , Low frequency modules need to provide low voltage. Then at this time, multi-voltage doma...

AI Technical Summary

Problems solved by technology

This makes the placement of the ISO unit very limited, and the flexibility is low

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