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A method and system for dynamic monitoring of data transmission between CPU and FPGA

A dynamic monitoring and data transmission technology, applied in the field of data transmission, can solve problems such as data loss and FPGA blocking, and achieve the effect of ensuring normal and reliable transmission and improving transmission rate

Active Publication Date: 2022-01-21
联想长风科技(北京)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In view of the defects in the prior art, the purpose of the embodiment of the present application is to provide a dynamic monitoring method and system for data transmission between the CPU and the FPGA, which solves the problems that often occur during the large data transmission between the CPU and the FPGA in the prior art. Technical issues with data loss during transmission due to FPGA backpressure / blocking issues

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  • A method and system for dynamic monitoring of data transmission between CPU and FPGA
  • A method and system for dynamic monitoring of data transmission between CPU and FPGA
  • A method and system for dynamic monitoring of data transmission between CPU and FPGA

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Embodiment 1

[0029] Such as figure 1 As shown, the embodiment of the present application provides a dynamic monitoring method for data transmission between CPU and FPGA, wherein the method includes:

[0030] Step S100: constructing a data transmission channel between the CPU and the FPGA;

[0031] Step S200: Obtain the first data packet on the CPU side, and perform initial dynamic marking to obtain the first dynamic marking;

[0032]Specifically, when large data is transmitted between the CPU and the FPGA, the back pressure / blocking problem of the FPGA often leads to data loss during the transmission process. In order to solve the problem of data packet loss, in the embodiment of this application, through Dynamic marking of data transmission between CPU and FPGA can effectively avoid the occurrence of such problems. Specifically, a data transmission channel between CPU and FPGA can be constructed, and the data transmission channel is used to transmit data between CPU and FPGA As the comp...

Embodiment 2

[0080] Based on the same inventive concept as a method for dynamic monitoring of data transmission between CPU and FPGA in the foregoing embodiments, the present invention also provides a dynamic monitoring system for data transmission between CPU and FPGA, such as Figure 8 As shown, the system includes:

[0081] The first construction unit 11: the first construction unit 11 is used to construct a data transmission channel between the CPU and the FPGA;

[0082] The first obtaining unit 12: the first obtaining unit 12 is used to obtain the first data packet at the CPU end, and perform initial dynamic marking to obtain the first dynamic marking;

[0083] The second obtaining unit 13: the second obtaining unit 13 is used to obtain the second data packet transmitted from the first data packet to the FPGA end based on the data transmission channel;

[0084] The first setting unit 14: the first setting unit 14 is used to set the data return response rule of the FPGA end;

[0085]...

Embodiment 3

[0121] Refer below Figure 9 An electronic device according to an embodiment of the present application will be described.

[0122] Figure 9 A schematic structural diagram of an electronic device according to an embodiment of the present application is shown.

[0123] Based on the inventive concept of a method for dynamic monitoring of data transmission between CPU and FPGA in the foregoing examples, the present invention also provides a dynamic monitoring system for data transmission between CPU and FPGA, on which a computer program is stored, and the program is executed by a processor When realizing the steps of any method of a CPU and FPGA data transmission dynamic monitoring system mentioned above.

[0124] Among them, in Figure 9 In, bus architecture (represented by bus 300), bus 300 may include any number of interconnected buses and bridges, bus 300 will include one or more processors represented by processor 302 and various types of memory represented by memory 304...

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Abstract

The invention discloses a method and system for dynamic monitoring of data transmission between CPU and FPGA, wherein the method includes: constructing a data transmission channel between CPU and FPGA; obtaining the first data packet at the CPU end, and performing initial dynamic marking to obtain First dynamic mark; Obtain the second data packet that described first data packet transmits to described FPGA end; Set the data return response rule of FPGA end; According to described data return response rule, obtain described FPGA end to the described The first return response sequence number of the second data packet, and return the dynamic mark to obtain the second dynamic mark; upload the first dynamic mark and the second dynamic mark to the data transmission dynamic monitoring system to obtain dynamic monitoring As a result, the data transfer between the CPU and the FPGA is dynamically monitored. It solves the technical problem of data loss during the transmission process that often occurs due to the back pressure / blocking problem of the FPGA in the prior art when large data is transmitted between the CPU and the FPGA.

Description

technical field [0001] The invention relates to the field of data transmission, in particular to a method and system for dynamic monitoring of data transmission between a CPU and an FPGA. Background technique [0002] In recent years, with the rapid development of social service informatization, data in various aspects such as the Internet, Internet of Things, finance, logistics, and electromagnetics have shown exponential growth. The transmission of big data is an important part of the basic process of big data processing. High-performance data transmission can provide guarantee for subsequent data analysis, especially real-time analysis. [0003] However, in the process of realizing the technical solution of the invention in the embodiment of the present application, the inventor of the present application found that the above-mentioned technology has at least the following technical problems: [0004] In the prior art, when large data is transmitted between the CPU and t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/30G06F13/20G06F15/163
CPCG06F11/3041G06F13/20G06F15/163
Inventor 谢元睿史晓岩
Owner 联想长风科技(北京)有限公司
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