Check patentability & draft patents in minutes with Patsnap Eureka AI!

Semiconductor packaging structure and manufacturing method thereof

A packaging structure, semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as easy peeling, reduced number of I/O, low bonding force, etc., to reduce peeling risk, increase heat dissipation efficiency, and reduce the effect of contact area

Pending Publication Date: 2021-11-05
ADVANCED SEMICON ENG INC
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] like figure 2 As shown, if the redistribution layer 3 is directly fabricated on the molding layer 4 without using the dielectric layer 7, the bonding force between the molding layer 4 and the redistribution layer 3 is low, and peeling (peeling) is likely to occur, so the product is reliable. sexually risky
[0004] Additionally, if Figure 4 As shown, if the distance between the existing lead frame 6 and the chip 1 is reduced, the contact area between the redistribution layer 3 and the molding layer 4 is minimized, although the poor bonding force between the redistribution layer 3 and the molding layer 4 can be improved. risk, but if Figure 5 As shown, the number of fan-out I / Os will be greatly reduced, and the product development space will be limited. Therefore, reducing the distance between the existing lead frame 6 and the chip 1 is not the best choice.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor packaging structure and manufacturing method thereof
  • Semiconductor packaging structure and manufacturing method thereof
  • Semiconductor packaging structure and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0027] The specific implementation manners of the present disclosure will be described below in conjunction with the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by the present disclosure and the technical effects produced through the contents recorded in this specification. It should be understood that the specific embodiments described here are only used to explain related inventions, rather than to limit the invention. In addition, for the convenience of description, only the parts related to the related invention are shown in the drawings.

[0028] It should be noted that the structures, proportions, sizes, etc. shown in the accompanying drawings of the specification are only used to match the content recorded in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present disclosure. There are limited conditions, so it has...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a semiconductor packaging structure and a manufacturing method thereof. According to the semiconductor packaging structure and the manufacturing method thereof, an extension part jointed with a rewiring layer is added in a lead frame, and the extension part is used as the substrate of the rewiring layer, so that the contact area of the rewiring layer and a mold sealing layer is reduced, and the risk of stripping of the rewiring layer can be effectively reduced.

Description

technical field [0001] The present disclosure relates to the field of semiconductor technology, in particular to a semiconductor package structure and a manufacturing method thereof. Background technique [0002] The fan out (fan out, also known as RDL redistribution layer) process based on the existing lead frame 6 (Lead Frame), such as figure 1 As shown, usually the I / O connections of the chip 1 are connected through vias or pillars. The redistribution layer 3 is usually formed on the dielectric layer 7, but the cost of this method is relatively high. [0003] Such as figure 2 As shown, if the redistribution layer 3 is directly fabricated on the molding layer 4 without using the dielectric layer 7, the bonding force between the molding layer 4 and the redistribution layer 3 is low, and peeling (peeling) is likely to occur, so the product is reliable. Sex can be risky. [0004] Additionally, if Figure 4 As shown, if the distance between the existing lead frame 6 and ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/495H01L23/488H01L21/50
Inventor 施佑霖李志成
Owner ADVANCED SEMICON ENG INC
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com