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Method of manufacturing semiconductor device and method of manufacturing power conversion device

A technology of a power conversion device and a manufacturing method, which is applied in the manufacture of semiconductor/solid-state devices, semiconductor devices, circuits, etc., can solve the problems of temperature rise of semiconductor elements and degradation of semiconductor element characteristics.

Pending Publication Date: 2021-11-12
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the temperature of the semiconductor element may rise during the operation of the semiconductor element, and the characteristics of the semiconductor element including the above-mentioned wide bandgap semiconductor may be degraded.

Method used

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  • Method of manufacturing semiconductor device and method of manufacturing power conversion device
  • Method of manufacturing semiconductor device and method of manufacturing power conversion device
  • Method of manufacturing semiconductor device and method of manufacturing power conversion device

Examples

Experimental program
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no. 1 Embodiment approach

[0044] Next, the semiconductor device and the method of manufacturing the semiconductor device according to the present embodiment will be described. For convenience of description, first, techniques related to the structure of a semiconductor device known to the inventors will be described.

[0045] Figure 16 It is a cross-sectional view schematically showing an example of the structure of a semiconductor device known to the inventor. Such as Figure 16 As illustrated, the semiconductor device has an insulating substrate 1, a plurality of upper surface metal patterns 1a formed on the upper surface of the insulating substrate 1, usually a single lower surface metal pattern 1b formed on the lower surface of the insulating substrate 1, and The semiconductor element 2 is bonded to the upper surface of the upper surface metal pattern 1a via a bonding material 3a such as solder.

[0046] The lower surface metal pattern 1b is bonded to the upper surface of the base plate 4 with ...

no. 2 Embodiment approach

[0079] The semiconductor device and the method of manufacturing the semiconductor device according to the present embodiment will be described. In addition, in the following description, the same structural elements as those described in the above-mentioned embodiment are attached with the same reference numerals and shown in figures, and the detailed description thereof is appropriately omitted.

[0080]

[0081] Figure 10 It is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to this embodiment. Figure 11 yes means Figure 10 A plan view of an example of the structure of the thermally conductive jig 5A illustrated in .

[0082] Such as Figure 10 As illustrated, the semiconductor device has an insulating substrate 1, a plurality of upper surface metal patterns 1a formed on the upper surface of the insulating substrate 1, a lower surface metal pattern 1b formed on the lower surface of the insulating substrat...

no. 3 Embodiment approach

[0088] The semiconductor device and the method of manufacturing the semiconductor device according to the present embodiment will be described. In addition, in the following description, the same structural elements as those described in the above-mentioned embodiment are attached with the same reference numerals and shown in figures, and the detailed description thereof is appropriately omitted.

[0089]

[0090] Figure 13 It is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to this embodiment. Figure 14 yes means Figure 13 A plan view of an example of the structure of the thermally conductive jig 5B illustrated in .

[0091] Such as Figure 13 As illustrated, the semiconductor device has an insulating substrate 1, a plurality of upper surface metal patterns 1a formed on the upper surface of the insulating substrate 1, a lower surface metal pattern 1b formed on the lower surface of the insulating substrat...

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Abstract

The application relates to a method of manufacturing a semiconductor device and a method of manufacturing a power conversion device. The occurrence of solder shrinkage holes directly under an insulating substrate at the position of a semiconductor element is suppressed. In the method of manufacturing the semiconductor device, a semiconductor element is bonded to the upper surface of the insulating substrate via first bonding material. A heat dissipation plate is joined to the lower surface of the insulating substrate via second bonding material. A heat conducting fixture is arranged in contact with the lower surface of the heat dissipation plate. The first bonding material and the second bonding material are heated and the heat conducting fixture is cooled in the state that the heat conducting fixture is in contact with the lower surface of the heat dissipation plate. The heat conducting fixture has a low heat conducting part. The low heat conducting part is arranged at a position that does not overlap the semiconductor element in a plan view, and has a lower heat conductivity than other parts of the heat conduction fixture.

Description

technical field [0001] The technology disclosed in this specification relates to a method of manufacturing a semiconductor device and a method of manufacturing a power conversion device. Background technique [0002] As a semiconductor device, there is a semiconductor device having an insulating substrate, a plurality of upper surface metal patterns formed on the upper surface of the insulating substrate, a lower surface metal pattern formed on the lower surface of the insulating substrate, and an upper surface metal pattern formed by a bonding material. Pattern the upper surface of the bonded semiconductor element. [0003] Among the above, the lower surface metal pattern is bonded to the upper surface of the base plate with cooling fins through the bonding material. In addition, the case housing the semiconductor element is bonded to the upper surface of the base plate with cooling fins via an adhesive. [0004] In addition, electrode terminals are connected to the upper...

Claims

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Application Information

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IPC IPC(8): H01L21/60H01L21/50
CPCH01L24/81H01L24/83H01L2224/81097H01L2224/81098H01L2224/83097H01L2224/83098
Inventor 石川悟
Owner MITSUBISHI ELECTRIC CORP
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