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Logic error correction method and circuit, computer chip and Internet-of-Things chip

A technology of error correction circuit and error correction method, applied in the computer field, can solve problems such as large resource overhead and reduced advantages of in-memory computing

Active Publication Date: 2021-11-26
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the resource overhead of the existing technology is still relatively large, and the advantages of in-memory computing are reduced

Method used

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  • Logic error correction method and circuit, computer chip and Internet-of-Things chip
  • Logic error correction method and circuit, computer chip and Internet-of-Things chip
  • Logic error correction method and circuit, computer chip and Internet-of-Things chip

Examples

Experimental program
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Embodiment 1

[0051] In the first aspect, the present application provides a logic error correction method, which is applied to a logic error correction circuit, and the logic error correction circuit includes: a first memristor, a second memristor, a third memristor and a fourth memristor Resistor; the first end of each memristor is respectively connected to the corresponding excitation voltage input end; the second end of each memristor is sequentially connected to the same bit line; the first memristor and the second memristor Two memristors form an IMP logical operation unit; the first memristor, the second memristor and the third memristor form a first or non-logical operation unit; the first memristor, The second memristor and the fourth memristor form a second or non-logic operation unit; the first or non-logic operation unit and the second or non-logic operation unit form an or non-logic detection unit; The second memristor, the three memristors and the fourth memristor form an OR l...

Embodiment 2

[0118] This embodiment provides a logic error correction circuit, and the circuit includes: first to fourth memristors and auxiliary resistors; the first memristor, the second memristor, the third memristor and the fourth memristor The first end of each memristor is respectively connected to the corresponding excitation voltage input end; the second end of each memristor is connected to the same bit line in sequence; the first end of each memristor is connected to the second The memristor forms an IMP logical operation unit; the first memristor, the second memristor and the third memristor form a first or non-logical operation unit; the first memristor, the The second memristor and the fourth memristor form a second or non-logic operation unit; the first or non-logic operation unit and the second or non-logic operation unit form an or non-logic detection unit; The second memristor, the third memristor and the fourth memristor form an OR logical operation unit;

[0119] The IM...

Embodiment 3

[0126] The present application provides a computer chip, comprising the logic error correction circuit described in any one of the above-mentioned embodiment 2, or performing logic error correction processing according to the logic error correction method described in any one of the above-mentioned embodiment 1.

[0127] For specific implementation steps, please refer to the relevant descriptions of the logic error correction circuit provided in the above-mentioned embodiment 2 and the logic error correction method provided in the embodiment 1. To avoid repetition, details are not repeated here.

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PUM

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Abstract

The embodiment of the invention discloses a logic error correction method and circuit, a computer chip and an Internet-of-Things chip, applied to a logic error correction circuit, the logic error correction circuit comprises an IMP logic operation unit, an NOR logic detection unit and an OR logic operation unit; the method comprises the following steps: according to four groups of initial logic combinations of the IMP logic operation unit and a high-low resistance state conversion condition, determining a target logic combination with a high-low resistance state conversion error result; enabling the NOR logic detection unit to detect a logic output result of the target logic combination and judging whether a logic error is generated or not according to the logic output result; and if the logic error is generated, enabling the OR logic operation unit to correct the logic error. According to the memristor-based logic error correction method, an appropriate excitation voltage is selected, a logic error occurrence rule is regulated and controlled, two types of specific logic elements are used, detection and correction of logic errors are completed in a logic cascade mode, and the memristor-based logic error correction method with low resource overhead is provided.

Description

technical field [0001] The present invention relates to the technical field of computers, in particular to a logic error correction method, a circuit, a computer chip and an Internet of Things chip. Background technique [0002] A memristor is a nonlinear resistor with a memory function. By controlling the change of the current, the resistance value of the memristor can be changed, and the function of storing data can be realized by the definition of high and low resistance states. Memristors have the characteristics of non-volatile characteristics, high integration, and high compatibility with CMOS, showing a wide range of application prospects. [0003] Due to the current fabrication process and other problems, there are many non-ideal factors in the memristor, such as fluctuations in the resistance value and fluctuations in the voltage transition threshold, which lead to unexpected errors in the actual operation of the memristor state logic. Aiming at the problems exist...

Claims

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Application Information

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IPC IPC(8): G06F11/07G11C13/00G11C29/52
CPCG06F11/073G06F11/0793G11C13/0021G11C29/52
Inventor 李智炜王义楠刘海军龙泓昌李清江刁节涛徐晖陈长林刘森宋兵王伟于红旗朱熙王玺步凯王琴曹荣荣
Owner NAT UNIV OF DEFENSE TECH
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