Digital layout disposition method and device in digital-analog hybrid circuit

Abstract

The invention discloses a digital layout disposition method and device in a digital-analog hybrid circuit. The method comprises the following steps: according to an obtained design netlist and design rules of a used technology, respectively determining a logic unit with a maximum pin width value and a minimum layout wiring design rule, adding a protection ring to the logic unit, and constructing a first standard unit; according to the first standard unit and the minimum layout wiring design rule, adding protection rings to logic units recorded on the design netlist, and obtaining a standard unit library; calling the standard unit library according to each digital module in the digital-analog hybrid circuit to be laid out, constructing a layout module, and completing the layout of the digital layout in the digital-analog hybrid circuit. According to the method, standard units required in the digital-analog hybrid circuit can be called from the standard unit library, and the layout module is constructed and submitted to a top layer layout designer for chip layout planning, so that the problem that the chip design efficiency is reduced due to repeated iteration on layout design is solved.

Description

technical field [0001] The invention belongs to the field of digital-analog hybrid circuit design, in particular to a method and device for digital layout in a digital-analog hybrid circuit. Background technique [0002] In all circuits designed for analog signal and digital signal processing, analog-to-digital and digital-to-analog conversion are essential components, which creates analog signal to digital signal (ADC), digital signal to analog signal (DAC) Any system cannot do without it, and the current systems are almost all digital and analog mixed-signal systems, and different application scenarios require different ADCs and DACs. With the increasing market demand, the length of the ADC and DAC chip development cycle, especially the design and implementation method, greatly affects its market share. Therefore, how to quickly complete its digital layout (Layout), reduce the area, and shorten the R&D cycle is particularly important. Among them, the layout of the digital...

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Problems solved by technology

However, this method is not conducive to the collaborative work of multiple layout engineers. For some logic units that may be reused in digital-analog hybrid circuits, such as INV (inverter), NAND (NAND gate), etc., layout engineers cannot Good processing prevents these logic units from being called repeatedly, which will increase the repeated iterations of layout design, affect the chip design cycle, and reduce the efficiency of chip design

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