Method and device for digital layout layout in digital-analog hybrid circuit
A technology of digital-analog mixing and layout, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of increasing layout design iterations, logic units that cannot be called repeatedly, and reducing chip design efficiency. Design efficiency, shorten chip tape-out time, good latch-up effect
Active Publication Date: 2022-06-03
广芯微电子(广州)股份有限公司
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However, this method is not conducive to the collaborative work of multiple layout engineers. For some logic units that may be reused in digital-analog hybrid circuits, such as INV (inverter), NAND (NAND gate), etc., layout engineers cannot Good processing prevents these logic units from being called repeatedly, which will increase the repeated iterations of layout design, affect the chip design cycle, and reduce the efficiency of chip design
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[0040] In order to make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments, and are not intended to limit the present invention. Based on the embodiments of the present invention, other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
[0041] seefigure 1 , which is a method for digital layout layout in a digital-analog hybrid circuit provided by an embodiment of the present invention, and specifically includes the following steps:
[0042] S101: According to the acquired design netlist and the design rules of the used process, respectively ...
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The invention discloses a method and device for digital layout layout in a digital-analog hybrid circuit. The method includes: according to the obtained design netlist and the design rules of the used process, respectively determine the logic unit with the largest pin width value and the smallest layout Routing design rules, and add a guard ring to the logic unit to build the first standard unit; according to the first standard unit and the minimum layout routing design rules, add a guard ring to the logic unit recorded on the design netlist to create a standard Cell library; according to each digital module in the digital-analog hybrid circuit to be laid out, call the standard cell library to construct the layout module, and complete the layout of the digital layout in the digital-analog hybrid circuit. The invention can call standard cells required in the digital-analog hybrid circuit from the standard cell library, construct layout modules, and submit them to the top-level layout designer for planning chip layout, which solves the problem of repeated iterations in layout design, thereby reducing the efficiency of chip design .
Description
technical field [0001] The invention belongs to the field of digital-analog hybrid circuit design, and particularly relates to a method and device for digital layout layout in a digital-analog hybrid circuit. Background technique [0002] In all circuits designed to analog signal and digital signal processing, analog-to-digital and digital-to-analog conversion are essential components, which creates an analog signal to digital signal (ADC), digital signal to analog signal (DAC) It is inseparable from any system. The current systems are almost all digital and analog mixed-signal systems, and different application scenarios require different ADCs and DACs. With the increasing market demand, the length of the ADC and DAC chip research and development cycle, especially the design and implementation method, greatly affects its market share. Therefore, how to quickly complete its digital layout (Layout), reduce the area, and shorten the R&D cycle is particularly important, and th...
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IPC IPC(8): G06F30/392
CPCG06F30/392
Inventor 王锐谭钰鑫莫军王亚波李建军
Owner 广芯微电子(广州)股份有限公司