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Interconnection system

A technology of interconnection system and interconnection interface, applied in the direction of response error generation, resource allocation, program control design, etc., can solve problems such as bandwidth inconsistency, data congestion, transmission bandwidth not being fully utilized, etc., and achieve low latency , high space utilization, and high bandwidth utilization

Pending Publication Date: 2021-12-31
VIA ALLIANCE SEMICON CO LTD
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Problems solved by technology

[0003] However, the bandwidth of the high-speed serial bus (PCIE) at the transmission end or the reception end is usually inconsistent with the bandwidth of the transmission channel, resulting in data congestion and underutilization of the transmission bandwidth during data transmission.

Method used

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Embodiment Construction

[0042] The following description lists various embodiments of the present invention, but is not intended to limit the content of the present invention. The actual scope of the invention is defined by the scope of the patent application.

[0043] In the various embodiments listed below, the same or similar elements or components will be denoted by the same reference numerals.

[0044] The invention discloses a cross-chip interconnection system, which includes a plurality of packages and interconnection interfaces between the packages, and the packages are arranged to communicate with each other through the first interconnection interface. The following description will refer to the first interconnection interface as ZPI.

[0045] figure 1 It is a structural schematic diagram of an example system 10 shown according to an embodiment of the present invention. Such as figure 1 As shown, system 10 contains two packages: socket0 and socket1, and a ZPI between them. Encapsulation...

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Abstract

An interconnection system includes a plurality of packages and a first interconnection interface. Any two of the packages can access hardware resources of each other by transmitting the first packet and the second packet through the first interconnection port. The first packet contains first interconnect information to establish communication between the two packages. The second packet includes a first data load loaded from one of the two packages. The package includes a first package and a second package, the first package and the second package being arranged to be connected to each other through a first interconnect interface.

Description

technical field [0001] The present invention relates to the field of integrated circuits (ICs), and in particular to interconnection systems including multiple sockets and interconnection ports. Background technique [0002] Traditional cross-chip transmission is realized by high-speed serial bus (PCIE). [0003] However, the bandwidth of the high-speed serial bus (PCIE) at the transmission end or the reception end is usually inconsistent with the bandwidth of the transmission channel, resulting in problems of data congestion and underutilization of the transmission bandwidth during data transmission. [0004] In addition, while taking data transmission performance into consideration, fine line design and ultimate space utilization between chips are also important issues. [0005] Therefore, there is a need for a cross-chip interconnection system with low latency, high bandwidth utilization and high space utilization. Contents of the invention [0006] An embodiment of t...

Claims

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Application Information

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IPC IPC(8): G06F13/40G06F11/10G06F9/50
CPCG06F13/4068G06F11/1004G06F9/5011G06F9/5016G06F9/505
Inventor 王惟林康潇亮张学敏陈晨石阳
Owner VIA ALLIANCE SEMICON CO LTD
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