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Semiconductor device and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of increased number of processes, high consistency, and deterioration of the wettability of memory chips.

Pending Publication Date: 2022-01-07
KIOXIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, since the spacer chip is used, the assembly cost becomes higher, and the number of steps increases
Furthermore, it is difficult to make the height of the controller chip and the spacer chip equal, and if a step occurs, the wettability of the memory chip at the bottom layer will deteriorate
In addition, the mold fillability of the tunnel part may deteriorate

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

no. 1 approach

[0035] figure 1 It is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 includes a wiring board 10 , semiconductor chips 20 , 30 to 33 , adhesive layers 40 to 43 , a metal material 70 , a resin layer 80 , a bonding wire 90 , and a sealing resin 91 . The semiconductor device 1 is, for example, a package of a NAND-type flash memory.

[0036] The wiring board 10 may be a printed board or an interposer including the wiring layer 11 and the insulating layer 15 . For the wiring layer 11 , low-resistance metals such as copper, nickel, or alloys thereof are used, for example. For the insulating layer 15, an insulating material such as glass epoxy resin is used, for example. In the drawing, the wiring layer 11 is provided only on the front and back surfaces of the insulating layer 15 . However, the wiring board 10 may have a multilayer wiring structure in which a plurality of wiring lay...

no. 2 approach

[0076] Figure 13A as well as Figure 13B It is a figure explaining the semiconductor device 1 of 3rd Embodiment. The second embodiment differs from the first embodiment in that the position of the semiconductor chip 30 is shifted (offset). Figure 13A as well as Figure 13B Each is a plan view showing an example of the positional relationship between the semiconductor chip 30 and the resin layer 80 . In addition, the upper surface S is omitted. in addition, Figure 13A as well as Figure 13B The illustrated resin layer 80 protrudes outward from the entire outer edge 30 o of the semiconductor chip 30 .

[0077] exist Figure 13A In the illustrated example, the center position of the semiconductor chip 30 substantially coincides with the center position of the semiconductor chip 20 and the center position of the resin layer 80 . on the other hand, Figure 13B The semiconductor chip shown is 30 ratios Figure 13A The illustrated semiconductor chip 30 is arranged so as ...

no. 3 approach

[0083] Figure 14A as well as Figure 14B It is a figure explaining the semiconductor device 1 of 3rd Embodiment. The third embodiment is different from the first embodiment in that an adjusted amount of the material 80 a of the resin layer 80 is applied on the wiring board 10 . Figure 14A It is a figure which shows an example of the material 80a of the resin layer 80 when the coating amount is small. exist Figure 14A Among them, the upper layer shows a cross-sectional view, and the lower layer shows a plan view. Figure 14B It is a figure which shows an example of the material 80a of the resin layer 80 when the coating amount is large. exist Figure 14B Among them, the upper layer shows a cross-sectional view, and the lower layer shows a plan view.

[0084] Figure 14A as well as Figure 14B The top view shows Figure 9 The coating process of the material 80a. exist Figure 14A as well as Figure 14B In the example shown, the material 80a is apply|coated in an X...

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PUM

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Abstract

A semiconductor device includes a wiring board; a first semiconductor chip including a first surface, a second surface, and a connection bump on the first surface, the first semiconductor chip coupled to the wiring board through the connection bump; a resin layer covering the connection bump between the first semiconductor chip and the wiring board, an upper surface of the resin layer parallel to the second surface of the first semiconductor chip; and a second semiconductor chip including a third surface, a fourth surface, and an adhesive layer on the third surface, the second semiconductor chip adhering to the second surface of the first semiconductor chip and the upper surface of the resin layer through the adhesive layer. The upper surface of the resin layer projects outside a portion of at least an outer edge of the second semiconductor chip when viewed from the top.

Description

[0001] Citations to Related Applications [0002] This application is based on, and seeks the benefit of, priority based on the prior Japanese Patent Application No. 2020-116296 for which it applied on Jul. 6, 2020, the entire contents of which are incorporated herein by reference. technical field [0003] The present embodiment relates to a semiconductor device and a method for manufacturing the same. Background technique [0004] As a package structure of a semiconductor device, there is known a structure in which a memory chip(s) are stacked over a controller chip that is flip-chip-connected to a substrate. For example, there is known a spacer structure in which a spacer chip is provided around a controller chip, and a memory chip is supported by the controller chip and the spacer chip. [0005] However, since the spacer chip is used, the assembly cost is increased, and the number of steps is increased. Furthermore, it is difficult to make the heights between the contro...

Claims

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Application Information

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IPC IPC(8): H01L25/18H01L23/31H01L21/56
CPCH01L25/18H01L23/3128H01L21/56H01L2224/32145H01L2224/32225H01L2224/48145H01L2224/48227H01L2224/16227H01L2224/73265H01L2224/73253H01L2225/0651H01L2225/06506H01L2225/06558H01L2225/06517H01L2225/06562H01L2225/06586H01L2924/15311H01L2224/16237H01L2224/48228H01L2224/73204H01L2224/83192H01L25/0657H01L25/50H01L2924/1431H01L2924/1438H01L2224/0401H01L2224/04042H01L23/49822H01L23/3135H01L21/6836H01L2221/68327H01L2221/6834H01L21/563H01L2224/83191H01L2924/00014H01L2224/48091H01L24/83H01L2224/83001H01L2924/181H01L24/32H01L24/73H01L2224/13082H01L2224/81001H01L2224/83194H01L24/16H01L2224/16225H01L2924/18161H01L24/48H01L2224/92125H01L2924/15174H01L24/92H01L2924/00012H01L2924/00H01L2224/45099H01L2224/16145H01L24/30H01L2224/27515H01L24/13H01L24/27H01L23/293H01L2224/1369H01L2224/13551H01L2224/1357H01L2224/30104H01L2224/30515H01L2224/3003H01L23/5383
Inventor 丹羽惠一
Owner KIOXIA CORP
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