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Parallel computing optimization method based on single-core DSP

A technology of parallel computing and optimization methods, applied in computing, concurrent instruction execution, program control design, etc., can solve the problems of large amount of image data processing, long algorithm running time, etc., to improve the parallelism of instruction execution and visual odometry algorithm. The effect of improved performance

Pending Publication Date: 2022-01-14
BEIJING INST OF CONTROL ENG
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Problems solved by technology

During the autonomous inspection process, the navigation control unit of the GNC subsystem of the Mars rover needs to run key complex algorithms such as navigation image processing, obstacle avoidance image processing, path autonomous planning, visual odometry, and motion control. long time problem

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  • Parallel computing optimization method based on single-core DSP

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Embodiment Construction

[0023] In order to make the object, technical solution and advantages of the present invention clearer, the implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0024] A parallel computing optimization method based on single-core DSP, firstly, to improve the parallelism of storage access, to achieve the purpose of fetching multiple program instructions at one time; then, on the basis of obtaining multiple instructions, to improve the parallelism of instruction execution , so that multiple instructions can be executed in parallel; finally, the parallelism of data processing is improved, and when one instruction is executed, the instruction can process multiple data at the same time. The specific implementation process is as figure 1 Shown:

[0025] 1) The first big step: improve the parallelism of storage access. Based on the characteristics of the hierarchical memory structure of the DSP pro...

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Abstract

A parallel computing optimization method based on a single-core DSP comprises the following steps that programs to be operated are divided into key complex programs and non-key complex programs, the key complex programs are fixedly operated in an internal cache of the DSP, and the non-key complex programs are operated in an external-configured RAM; in loop statements in the to-be-run program, a loop counter is made to be decreased progressively, and loop nesting is not conducted in a loop body; hardware resources used by each loop body do not exceed the number of arithmetic units and the number of registers in the processor, so that statements in each loop body can be executed in parallel in the multiple arithmetic units at the same time; and a single-instruction multi-data instruction is adopted to perform assembly programming on the data subjected to the same calculation processing, so that the parallelism degree of data processing is improved.

Description

technical field [0001] The invention relates to a single-core DSP-based parallel computing optimization method, which belongs to the technical field of on-board computers. Background technique [0002] my country's first Mars exploration achieved the goal of "circling, landing, and patrolling" Mars through a single flight mission. The landing patrol "Zhu Rong" Mars rover broke through key technologies such as safe and autonomous patrols on the surface of Mars. During the autonomous inspection process, the navigation control unit of the GNC subsystem of the Mars rover needs to run key complex algorithms such as navigation image processing, obstacle avoidance image processing, path autonomous planning, visual odometry, and motion control. long problem. Therefore, in order to meet the autonomous, safe, and efficient inspection requirements of the Mars rover, it is necessary to optimize the various complex algorithms on the navigation control unit in parallel to improve the ope...

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Application Information

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IPC IPC(8): G06F9/38G06F12/0884
CPCG06F12/0884G06F9/3885
Inventor 苗志富陈建新周育逵彭飞刘超伟刘波韩朝君张琳王玉陈玙
Owner BEIJING INST OF CONTROL ENG
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