Analog memory operational circuit
A computing circuit and memory technology, which is applied in the field of analog memory computing circuits, can solve the problems of increased area, limited number of memory unit computing bits, difficulty in multi-level storage of NOR flash memory, etc., to achieve good computing power and reduce area Effect
Pending Publication Date: 2022-01-14
2X MEMORY TECH CORP
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Problems solved by technology
When more computing layers are required, more groups of computing circuits are required, resulting in an increase in the area
[0005] The known computing circuit 20 uses NOR flash memory to store weight data, but it is difficult for NOR flash memory to realize multi-level storage (multi-level cell), so the number of bits for memory unit operation is limited
In addition, NOR flash memory has reached a bottleneck in terms of process miniaturization and operating speed.
Method used
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[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
[0028] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0029] Figure 4 It is the first embodiment of the simulated memory operation circuit provided by the present invention. Figure 4 The analog memory operation circuit 30 includes a plurality of input circuits 31 ...
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The invention provides an analog memory operation circuit which comprises at least one input circuit, at least one output circuit and at least one analog memory operation unit. Each analog memory arithmetic unit is connected between one of the at least one input circuit and one of the at least one output circuit, and has at least one weight mode. Each analog memory operation unit performs operation according to the weight of the selected weight mode and at least one input signal of the input circuit connected with the analog memory operation unit so as to generate at least one first operation result on the at least one output end to the output circuit connected with the analog memory operation unit.
Description
technical field [0001] The invention relates to an analog memory operation circuit. Background technique [0002] In traditional computer architecture10, such as figure 1 As shown, the processor 16 obtains data from the memory 12 through the bus 14 and performs calculations. However, as the processing speed of the processor 16 increases, the transmission speed of the bus 14 cannot keep up with the processing speed of the processor 16. Therefore, when the processor 16 finishes computing a piece of data, the bus 14 cannot transfer the next data in real time. After the data transmission is complete, the processor 16 needs to wait for a period of time before performing calculations on the next data. In other words, the computing capability of the computer architecture 10 is limited by the bus bar 14 and cannot be improved. Since the AI circuit requires a large number of Multiply Accumulate (MAC) operations, the traditional computer architecture 10 is no longer suitable for ...
Claims
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IPC IPC(8): G11C11/16G11C13/00
CPCG11C11/165G11C13/0021G11C7/1006G11C13/004G11C7/16G11C13/0002G11C11/56G11C11/54G11C11/16G11C7/109G11C7/1063G11C5/06G11C7/1069G11C7/1096G11C7/10
Inventor 陈立哲刘承杰叶恒诚
Owner 2X MEMORY TECH CORP