A heterojunction cell with improved photoelectric conversion efficiency
A technology of photoelectric conversion efficiency and heterojunction cells, applied in photovoltaic power generation, circuits, electrical components, etc., can solve the problem that the photogenerated current of HJT cells cannot be further improved, and achieve high conversion efficiency
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Embodiment 1
[0035] First, the textured n-type silicon substrate 1 is selected to prepare the textured surface, that is, a pyramid-shaped light trapping structure is constructed on the surface of the n-type silicon substrate 1;
[0036] Next, deposition of intrinsic amorphous silicon 2 on the backside of the n-type silicon substrate 1;
[0037] Secondly, the deposition of doped amorphous silicon is performed on the intrinsic amorphous silicon 2 on the back side;
[0038] Then, deposition of intrinsic amorphous silicon 2 is performed on the front surface of the n-type silicon substrate 1;
[0039] Then, a hard mask method is used to deposit a mixed layer 3 on the front side of the battery, and the thickness of the mixed layer 3 is 9 nm; wherein, when the doped amorphous silicon in S3 is selected as the first n-type doped amorphous In the case of silicon 6, the mixed layer 3 is a first p-type doped amorphous silicon 30 and film layer 31; when the doped amorphous silicon in S3 is selected ...
Embodiment 2
[0043] First, the textured n-type silicon substrate 1 is selected to prepare the textured surface, that is, a pyramid-shaped light trapping structure is constructed on the surface of the n-type silicon substrate 1;
[0044] Next, deposition of intrinsic amorphous silicon 2 on the backside of the n-type silicon substrate 1;
[0045] Secondly, the deposition of doped amorphous silicon is performed on the intrinsic amorphous silicon 2 on the back side;
[0046] Then, deposition of intrinsic amorphous silicon 2 is performed on the front surface of the n-type silicon substrate 1;
[0047] Then, a hard mask method is used to deposit a mixed layer 3 on the front side of the battery, and the thickness of the mixed layer 3 is 5 nm; wherein, when the doped amorphous silicon in S3 is selected as the first n-type doped amorphous In the case of silicon 6, the mixed layer 3 is a first p-type doped amorphous silicon 30 and film layer 31; when the doped amorphous silicon in S3 is selected ...
Embodiment 3
[0051] First, the textured n-type silicon substrate 1 is selected to prepare the textured surface, that is, a pyramid-shaped light trapping structure is constructed on the surface of the n-type silicon substrate 1;
[0052] Next, deposition of intrinsic amorphous silicon 2 on the backside of the n-type silicon substrate 1;
[0053] Secondly, the deposition of doped amorphous silicon is performed on the intrinsic amorphous silicon 2 on the back side;
[0054] Then, deposition of intrinsic amorphous silicon 2 is performed on the front surface of the n-type silicon substrate 1;
[0055] Then, a hard mask method is used to deposit a mixed layer 3 on the front side of the battery, and the thickness of the mixed layer 3 is 1 nm; wherein, when the doped amorphous silicon in S3 is selected as the first n-type doped amorphous In the case of silicon 6, the mixed layer 3 is a first p-type doped amorphous silicon 30 and film layer 31; when the doped amorphous silicon in S3 is selected ...
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