Heterojunction cell with improved photoelectric conversion efficiency
A technology of photoelectric conversion efficiency and heterojunction cells, applied in photovoltaic power generation, circuits, electrical components, etc., can solve the problem that the photo-generated current of HJT cells cannot be further improved, and achieve high conversion efficiency
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Embodiment 1
[0035] Firstly, the textured n-type silicon substrate 1 is selected, and the textured surface is prepared, that is, a pyramid-shaped light-trapping structure is constructed on the surface of the n-type silicon substrate 1;
[0036] Next, the deposition of intrinsic amorphous silicon 2 on the back side of the n-type silicon substrate 1;
[0037] Second, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back;
[0038] Then, deposit intrinsic amorphous silicon 2 on the front side of the n-type silicon substrate 1;
[0039] Then, use the hard mask plate method to deposit the mixed layer 3 on the front of the battery, the thickness of the mixed layer 3 is 9nm; wherein, when the doped amorphous silicon in S3 is selected as the first n-type doped amorphous silicon Silicon 6, the mixed layer 3 is the first p-type doped amorphous silicon 30 and Film layer 31; when the doped amorphous silicon in S3 is selected as the second p-type doped amorphous silicon ...
Embodiment 2
[0043] Firstly, the textured n-type silicon substrate 1 is selected, and the textured surface is prepared, that is, a pyramid-shaped light-trapping structure is constructed on the surface of the n-type silicon substrate 1;
[0044] Next, the deposition of intrinsic amorphous silicon 2 on the back side of the n-type silicon substrate 1;
[0045] Second, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back;
[0046] Then, deposit intrinsic amorphous silicon 2 on the front side of the n-type silicon substrate 1;
[0047] Then, use the hard mask plate method to deposit the mixed layer 3 on the front of the battery, the thickness of the mixed layer 3 is 5nm; wherein, when the doped amorphous silicon in S3 is selected as the first n-type doped amorphous silicon Silicon 6, the mixed layer 3 is the first p-type doped amorphous silicon 30 and Film layer 31; when the doped amorphous silicon in S3 is selected as the second p-type doped amorphous silicon ...
Embodiment 3
[0051] Firstly, the textured n-type silicon substrate 1 is selected, and the textured surface is prepared, that is, a pyramid-shaped light-trapping structure is constructed on the surface of the n-type silicon substrate 1;
[0052] Next, the deposition of intrinsic amorphous silicon 2 on the back side of the n-type silicon substrate 1;
[0053] Second, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back;
[0054] Then, deposit intrinsic amorphous silicon 2 on the front side of the n-type silicon substrate 1;
[0055] Then, use the hard mask plate method to deposit the mixed layer 3 on the front of the battery, the thickness of the mixed layer 3 is 1nm; wherein, when the doped amorphous silicon in S3 is selected as the first n-type doped amorphous Silicon 6, the mixed layer 3 is the first p-type doped amorphous silicon 30 and Film layer 31; when the doped amorphous silicon in S3 is selected as the second p-type doped amorphous silicon 6′, the ...
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