Device and method for realizing cross-clock-domain time domain convolution calculation based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a device and a method for realizing cross-clock-domain time domain convolution calculation based on an FPGA (Field Programmable Gate Array). The device comprises RAM (Random Access Memory) _coef, FIFO_coef and FIFO_conv which are realized based on the FPGA, the RAM_coef and the (M-1) FIFO_coef form a pipeline structure which is sequentially transmitted according to a signal time sequence, and the RAM_coef and the (M-1) FIFO_coef are respectively in one-to-one correspondence with the M multipliers and are used for respectively providing corresponding convolution coefficients for time sequence signals of the M multipliers; the M multiplying units and the corresponding adders work in parallel, before a next signal arrives, (M-1) intermediate results of multiplication and addition operation are generated, and M FIFOconvs are adopted to store the intermediate results of the multiplication and addition operation of the M signals respectively. The method can meet the application requirements of high real-time performance and less output delay, and has the characteristic of less resource consumption.

Description

technical field [0001] The invention belongs to the technical field of programmable device applications, and in particular relates to an FPGA-based time-domain convolution calculation device and method across clock domains. Background technique [0002] Convolution is widely used in engineering and mathematics. In statistics, a weighted moving average is a type of convolution. In probability theory, the probability density function of the sum of two statistically independent variables X and Y is the convolution of the probability density functions of X and Y. In electronic engineering and signal processing, the output of any linear system can be obtained by convolving the input signal with the system function (the system's impulse response). [0003] The convolution operation process can be regarded as a multiply-add operation. If the convolution coefficient is long, the FPGA will occupy more multiplier and adder resources when performing multiplication and addition opera...

AI Technical Summary

Problems solved by technology

[0006] In order to solve the problems of high delay and low real-time performance in the existing method of realizing convolution calculation on FPGA, the present invention provides a time-domain convolution calculation device based on FPGA to realize cross-clock domain

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