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Semiconductor capacitor structure and manufacturing method thereof, memory and electronic equipment

A technology of capacitor structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problems of reduced reliability, reduced capacitance of semiconductor capacitors, lower electrode damage, etc., and achieves high reliability. , the effect of avoiding the loss of capacitance

Pending Publication Date: 2022-02-18
INST OF MICROELECTRONICS CHINESE ACAD OF SCI +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In order to solve the problem that the conventional technology inevitably causes damage to the top of the lower electrode, and leads to the reduction of the capacitance and reliability of the semiconductor capacitor, the present disclosure provides a semiconductor capacitor structure and its manufacturing method, memory, and electronic equipment.

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  • Semiconductor capacitor structure and manufacturing method thereof, memory and electronic equipment
  • Semiconductor capacitor structure and manufacturing method thereof, memory and electronic equipment
  • Semiconductor capacitor structure and manufacturing method thereof, memory and electronic equipment

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Embodiment Construction

[0028] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0029] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, ...

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PUM

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Abstract

The invention provides a semiconductor capacitor structure and a manufacturing method thereof, a memory and electronic equipment. The capacitor structure comprises a semiconductor substrate, a plurality of welding pads distributed at intervals are formed on the semiconductor substrate, and the bottoms of lower electrodes are located on the welding pads. At least one layer of lower supporting piece and upper supporting piece are arranged between the side walls of the lower electrode, and the thickness of the lower electrode is uniformly distributed downwards from the top end of the lower electrode. The memory includes the semiconductor capacitor structure. The electronic equipment includes the memory. The manufacturing method includes: forming a first laminated layer and a second laminated layer on the semiconductor substrate. etching the second laminated layer and the first laminated layer to form a groove penetrating through the lower supporting layer and backfilling. etching the second laminated layer and the first laminated layer so as to form a capacitor hole and further form a lower electrode. and performing etching based on the groove to form the upper supporting piece and the lower supporting piece. According to the invention, the supporting layer etching process is carried out before the lower electrode is deposited, so that the problem that the lower electrode is damaged when the supporting layer is etched later in the conventional technology is solved.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductor devices, and more specifically, the present disclosure provides a semiconductor capacitor structure and a manufacturing method thereof, a memory, and an electronic device. Background technique [0002] The capacitor manufacturing process of Dynamic Random Access Memory (DRAM) is a contact process with a large aspect ratio. Wherein, after the node separation of the lower electrode is performed, the oxide molding layer can be removed by etching the support layer additionally. However, it is unavoidable to damage the top of the bottom electrode while etching the supporting layer. Such as Figure 9 As shown, the height of the conventional lower electrode after being damaged decreases, which in turn leads to the problem of capacitance loss (Csloss, Capacity storage loss) of the semiconductor capacitor. Moreover, the shape of the top of the conventional lower electrode becomes sharp, th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/108H01L21/8242H10B12/00
CPCH10B12/03H10B12/30
Inventor 全宗植吴容哲杨涛高建峰殷华湘
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI