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Multi-bit multiply-accumulate operation unit and in-memory calculation device

A computing unit and computing device technology, applied in computing, information storage, static memory, etc., can solve the problems of read and write interference, low precision, and many single-bit calculations, and achieve the effect of avoiding read and write interference

Active Publication Date: 2022-02-25
中科南京智能技术研究院
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In-memory computing (IMC) is becoming more and more attractive for DCNN acceleration. Traditional in-memory computing units mostly use voltage or level for calculation, and there are many single-bit calculations, which have the problems of read and write interference and low precision.

Method used

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  • Multi-bit multiply-accumulate operation unit and in-memory calculation device
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  • Multi-bit multiply-accumulate operation unit and in-memory calculation device

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Experimental program
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Embodiment 1

[0029] The present invention discloses a multi-bit multiplication and accumulation operation unit 1, and the multi-bit multiplication and accumulation operation unit 1 includes:

[0030] Computing units 6 in M ​​columns; the computing units 6 in each column include N computing subunits 7; wherein, M and N are positive integers greater than or equal to 1; each of the computing subunits in the memory 7 all include a 6T-SRAM storage unit, a switch tube M7 and a switch tube M8; the first end of the switch tube M7 is connected to the 6T-SRAM storage unit, the second end of the switch tube M7 is connected to the common terminal VSS, and the first end of the switch tube M7 The three terminals are connected with the second terminal of the switch tube M8, the first terminal of the switch tube M8 is used for inputting the pulse signal, and the third terminal of the switch tube M8 is used for outputting the read bit line signal.

[0031] As an optional implementation manner, the 6T-SRAM ...

Embodiment 2

[0037] Such as figure 2 As shown, the present invention also discloses an in-memory computing device. The in-memory computing device includes eight multi-bit multiplication and accumulation operation units 1, an input control module 2, a bit line driver module 3, and a word line driver module in Embodiment 1. 4 and 8 sets of multiplication and accumulation readout calculation modules 5; the input control module 2, the bit line driver module 3 and the word line driver module 4 are all connected to each of the multi-bit multiplication and accumulation operation units 1, the gth The multiply-accumulate readout calculation module 5 of the group is connected with the g-th multi-bit multiply-accumulate operation unit 1, and g is a positive integer greater than or equal to 1 and less than or equal to 8; the input control module 2 is used to input data converted into pulse signals In-In for output, and the bit line driver module 3 is used to output reverse bit line signals BLB0-BL...

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Abstract

The invention relates to a multi-bit multiply-accumulate operation unit and an in-memory calculation device. The multi-bit multiply-accumulate operation unit comprises M columns of in-memory calculation units, each column of in-memory calculation units comprises N in-memory calculation subunits; each in-memory calculation subunit comprises a 6T-SRAM (Static Random Access Memory) storage unit, a switching tube M7 and a switching tube M8; the first end of the switch tube M7 is connected with the storage unit, the second end of the switch tube M7 is connected with the common end, the third end of the switch tube M7 is connected with the second end of the switch tube M8, the first end of the switch tube M8 is used for inputting a pulse signal, and the third end of the switch tube M8 is used for outputting a read bit line signal. In the multiply-accumulate operation, the influence of read-write interference is avoided by additionally adding the switch tubes M7 and M8.

Description

technical field [0001] The invention relates to the technical field of in-memory computing, in particular to a multi-bit multiplication and accumulation operation unit and an in-memory computing device. Background technique [0002] Deep Convolutional Neural Networks (DCNNs) are developing rapidly in artificial intelligence and other fields. With its gradual development, it is necessary to consider more and more issues such as size, efficiency, and energy consumption. In the traditional calculation process, the weight is moved between the memory and the operation unit, which does not meet the requirements of low power consumption. In-memory computing (IMC) is becoming more and more attractive for DCNN acceleration. Traditional in-memory computing units mostly use voltage or level for calculation, and there are many single-bit calculations, which have problems of read and write interference and low precision. Contents of the invention [0003] The object of the present inv...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/523G06N3/063G11C16/08G11C16/24
CPCG06F7/5235G06N3/063G11C16/08G11C16/24
Inventor 乔树山陶皓尚德龙周玉梅
Owner 中科南京智能技术研究院