Data processing method and device, equipment, and readable storage medium

Abstract

The invention discloses a data processing method and device, equipment, and a readable storage medium. The method comprises the following steps: a target expression is converted into a data structure of a binary tree and a chain table; different FPGA cache regions are allocated to operands of all nodes of the data structure, and original nodes in the data structure are marked; then an original operand mapping table is created, an instruction is generated for each layer of the data structure; the original operand mapping table and the generated instructions are sent to the FPGA, and the FPGA copies the operand of each node to a corresponding FPGA cache region according to the original operand mapping table, and after the original operands in FPGA cache regions corresponding to the original nodes are read according to the generated instructions, operation codes in a same layer in the data structure are processed in parallel from a bottom layer of the data structure. Therefore, parallel processing is carried out on operation codes in the same layer, and the parallel processing efficiency of expressions is improved. The data processing device, the equipment, and the readable storage medium provided by the invention, also have the above technical effects.

Description

technical field [0001] The present application relates to the field of computer technology, and in particular to a data processing method, device, equipment and readable storage medium. Background technique [0002] In the traditional CPU (Central Processing Unit, central processing unit) coding scheme, the database can encode the expression into a data structure of a binary tree plus a linked list, and serially process the operation codes of each node by traversing the data structure of the binary tree plus a linked list . Although the CPU coding scheme can implement parallel processing of multiple opcodes in the node in SIMD (Single Instruction Multiple Data) mode for each node. However, for complex expressions, it is still necessary to execute opcodes one by one, and parallel processing of multiple opcodes cannot be realized. SIMD stands for Single Instruction Multiple Data, which operates multiple data in batches within one instruction. [0003] At present, FPGA (Fiel...

AI Technical Summary

Problems solved by technology

[0003] At present, FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array) can be used to increase the processing speed, but the existing FPGA solution for heterogeneous acceleration uses truth tables only for logical operation codes such as AND, OR, and NOT in parallel. processing, does not support the execution of expressions such as comparisons, calculations, etc.

In other solutions, fixed query statement templates are implemented in the FPGA to achieve heterogeneous acceleration, which cannot support dynamic changes in expressions, which limits the usage scenarios of FPGA heterogeneous acceleration.

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