A data processing method, device, equipment and readable storage medium

Abstract

The application discloses a data processing method, device, equipment and readable storage medium. After the application converts the target expression into a data structure of a binary tree plus a linked list, allocate different FPGA buffer areas for the operands of each node of the data structure, and mark the original nodes in the data structure; then create the original operand mapping Table, generate instructions for each layer of the data structure, send the original operand mapping table and the generated instructions to FPGA, FPGA copies the operand of each node to the corresponding FPGA buffer according to the original operand mapping table, and according to After the generated instruction reads the original operands in the FPGA buffer corresponding to the original node, the operation codes at the same layer in the data structure are processed in parallel from the bottom layer of the data structure, so that the operation codes of the same layer are processed in parallel, thus improving the Expression parallel processing efficiency. A data processing device, equipment, and readable storage medium provided by the present application also have the above-mentioned technical effects.

Description

technical field [0001] The present application relates to the field of computer technology, and in particular to a data processing method, device, equipment and readable storage medium. Background technique [0002] In the traditional CPU (Central Processing Unit, central processing unit) coding scheme, the database can encode the expression into a data structure of a binary tree plus a linked list, and serially process the operation codes of each node by traversing the data structure of the binary tree plus a linked list . Although the CPU coding scheme can implement parallel processing of multiple opcodes in the node in SIMD (Single Instruction Multiple Data) mode for each node. However, for complex expressions, it is still necessary to execute opcodes one by one, and parallel processing of multiple opcodes cannot be realized. SIMD stands for Single Instruction Multiple Data, which operates multiple data in batches within one instruction. [0003] At present, FPGA (Fiel...

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Problems solved by technology

[0003] At present, FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array) can be used to increase the processing speed, but the existing FPGA solution for heterogeneous acceleration uses truth tables only for logical operation codes such as AND, OR, and NOT in parallel. processing, does not support the execution of expressions such as comparisons, calculations, etc.

In other solutions, fixed query statement templates are implemented in the FPGA to achieve heterogeneous acceleration, which cannot support dynamic changes in expressions, which limits the usage scenarios of FPGA heterogeneous acceleration.

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