Decoupling SRAM (Static Random Access Memory) in-memory computing device

Abstract

The invention relates to a decoupling SRAM (Static Random Access Memory) in-memory computing device. The device comprises a middle column selection and bit line driving module which is connected with an SRAM (Static Random Access Memory) calculation unit array through bit lines BL and BLB; the input driving and pulse generating module is connected with the SRAM computing unit array through a multiply-accumulate word line (MWL); the word line driving and decoding module is connected with the SRAM calculation unit array through a word line WL; and the analog-to-digital converter array is connected with the SRAM calculation unit array through a multiply-accumulate bit line MBL and a multiply-accumulate bit line MBLB. According to the invention, read-write interference can be eliminated, the range of the quantized ADC can be expanded, and the pressure of ADC quantization precision is reduced.

Description

technical field [0001] The invention relates to the field of in-memory computing, in particular to a decoupling SRAM in-memory computing device. Background technique [0002] With the unprecedented growth in the size of deep neural networks (DNNs), large amounts of data in modern machine learning (ML) accelerators need to be moved from off-chip memory to on-chip processing cores. Computation-in-memory (CIM) designs that perform analog DNN computations in memory arrays, along with peripheral mixed-signal circuits, are currently being explored by the industry to alleviate this memory-wall bottleneck: memory latency and energy overhead. Monolithic integration of Static Random Access Memory (SRAM) bit cells with high-performance logic transistors and interconnects enables custom CIM designs. [0003] However, when doing multiplication and accumulation operations, the traditional on-chip SRAM needs to be accessed row by row. In order to reduce the delay and energy of on-chip SRA...

AI Technical Summary

Problems solved by technology

[0004] In the SRAM-based memory computing (IMC) scheme, the calculation method of single-bit input multiplied by single-bit weight is inefficient, and because the weight is connected to the source and drain of the calculation tube, the weight will be affected when the voltage swing of the bit line is too large during the calculation process. value; not only that, when multi-unit calculations, because the quantization range of the bit line voltage is too small, it is necessary to use a very accurate quantization comparator to achieve analog-to-digital conversion, and a high-precision analog-digital converter (Analog-Digital Converter, ADC ) is also non-trivial to design, otherwise it would lead to quantization errors

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