Comparator circuit capable of expanding input range

Abstract

The invention provides a comparator circuit capable of expanding an input range, and the comparator circuit comprises a first-stage comparison circuit which is connected with a power supply voltage VCC and is used for converting a differential voltage into a differential current; the second-stage comparison circuit is connected with the first-stage comparison circuit and is used for mirroring and comparing the differential current; the first common end of the first-stage comparison circuit and the second-stage comparison circuit is connected to the positive end voltage VP of a differential signal, and the second common end is connected to the negative end voltage VN; the upper end of the third-stage comparison circuit is connected with the second-stage comparison circuit, the lower end of the third-stage comparison circuit is connected to a circuit reference ground GND, and the third-stage comparison circuit is used for converting the voltage threshold of the power supply voltage VCC to the positive end voltage VP or the negative end voltage VN of the differential output voltage of the first-stage comparison circuit and the second-stage comparison circuit into the voltage threshold of the normal power supply voltage VCC to the circuit reference ground GND. The input of positive and negative voltage comparators is supported, the input range of a conventional comparator is expanded, and the common-mode input circuit has the characteristics of wide common-mode input range, high integration level, high flexibility and the like.

Description

technical field [0001] The present disclosure relates to the technical field of integrated circuits, in particular to a comparator circuit with an expandable input range. Background technique [0002] Conventional comparator circuits such as figure 1 As shown, where Vb provides the bias voltage of the tail current source, set the threshold voltage of the MOS tube as VTH, the voltage across the drain-source of the MOS tube as VDS, and the voltage across the gate-source of the MOS tube as VGS, then ensure that the PM1 tube does not enter the cut-off region The condition is: VP+V THPM1 ≤VCC-V DSPM3 ; Namely: VP≤VCC-V DSPM3 -V THPM1 ;The condition to ensure that the PM1 tube does not enter the linear region is: VP+V THPM1 ≥V GSNM1 , that is: VP≥V GSNM1 -V THPM1 . [0003] To sum up, the input range of the comparator VP is: VGSNM1-VTHPM1≤VP≤VCC-VDSPM3-VTHPM1. Generally speaking, if the threshold voltages of the PMOS transistor and the NMOS transistor are equal or close,...

AI Technical Summary

Problems solved by technology

Therefore, when the input voltage at both ends of the comparator is close to 0 or is a negative voltage, the traditional comparator cannot compare the magnitudes of the two well, or even compare the magnitudes of the two, which leads to the failure of the comparator circuit

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