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Video clamping circuit with low power consumption and large signal input range

A technology of signal range and clamping circuit, which is applied in the direction of TV, electrical components, color TV, etc., and can solve the problems of limited duration and small input current of the circuit

Active Publication Date: 2011-04-13
3PEAK INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] like figure 1 In the circuit shown, the circuit is also a clamping circuit, in which the transconductance amplifier NMOS2 tube and NMOS3 tube are connected to the filter, and the transconductance amplifier is also connected to other transistors, but the circuit can only input a small range and the current is continuously limited

Method used

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  • Video clamping circuit with low power consumption and large signal input range
  • Video clamping circuit with low power consumption and large signal input range
  • Video clamping circuit with low power consumption and large signal input range

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Embodiment Construction

[0015] Such as figure 2 As shown, the transconductance amplifier composed of PMOS1 and PMOS2 pair of tubes, the current mirror amplifier composed of PMOS3 tube and PMOS4 tube, the gate of the PMOS1 is connected to the reference voltage device (Vref), the reference voltage device is connected to the ground, and the PMOS1 The drain of the NMOS3 tube is connected to the source of the NMOS3 tube, and the drain of the NMOS3 tube is connected to the drain of the PMOS4.

[0016] Then the drain of the NMOS1 transistor is connected to the transconductance amplifier, the grid of the NMOS1 transistor is connected to the grid of the NMOS2 transistor, and the grid of the NMOS2 transistor is connected to the drain of the NMOS2 transistor. Such connection makes the NMOS1 and NMOS2 transistors become Constant current source load, NMOS3 is used as a common gate to match the drains of NMOS1 and NMOS2, ensuring that the current flowing through the two NMOS transistors at the same time is the sa...

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PUM

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Abstract

The invention discloses a video clamping circuit comprising a transconductance amplifier and a current mirror amplifier, wherein the transconductance amplifier consists of a PMOS (P-channel Metal Oxide Semiconductor) transistor 1 and a PMOS transistor 2 which are butted, and the current mirror amplifier consists of a PMOS transistor 3 and a PMOS transistor 4. The video clamping circuit is characterized in that the grid electrode of the PMOS transistor 1 is connected with a Vref (Voltage Reference Device), the Vref is connected with the ground, the drain electrode of the PMOS transistor 1 is connected with the source electrode of a NMOS (N-channel Metal Oxide Semiconductor) transistor 3, and the drain electrode of the NMOS transistor 3 is connected with the drain electrode of the PMOS transistor 4. The transconductance amplifier is also connected with a filter for filtering excessive signals. The video clamping circuit relates to a clamping circuit having the advantages of low power consumption and large signal input range.

Description

technical field [0001] The present invention relates to a video clamping circuit, in particular to a video clamping band circuit with large power consumption input signal. Background technique [0002] An analog TV signal is a composite signal consisting of phase and amplitude information, which conveys picture structure information in terms of DC values. During the video transmission signal, the DC reference value may be lost, so it is necessary to re-establish the reference value, requiring a video clamping circuit. In general, there are two categories of video clamping circuits. One of them is that the clamping circuit is activated in a predefined period per row, but it requires a timing signal or generating timing circuit. The other is an automatic clamping circuit, which is composed of a comparator with a control loop and does not require a timing signal, but this type of circuit is sensitive to changes in external parameters, and its stability is difficult to design....

Claims

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Application Information

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IPC IPC(8): H04N5/18
Inventor 刘扬应峰何德军周之栩牟陟
Owner 3PEAK INC
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