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Clock data recovery circuit and serial receiver

A clock data recovery and receiver technology, applied in the circuit field, can solve the problems of long CDR loop delay and slow response speed, and achieve the effects of improving work energy efficiency, reducing loop delay, and ensuring stability

Active Publication Date: 2022-05-06
高澈科技(上海)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved by the present invention is to provide a clock data recovery circuit and a serial receiver in order to overcome the defects of long CDR loop delay and slow response speed in the existing ADC-based serial receiver

Method used

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  • Clock data recovery circuit and serial receiver
  • Clock data recovery circuit and serial receiver
  • Clock data recovery circuit and serial receiver

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0032] This embodiment provides a clock data recovery circuit, such as figure 1 As shown, it includes a first clock data recovery unit, a second clock data recovery unit and a phase interpolator.

[0033] The first clock data recovery unit is used to collect high-order quantized data of the ADC, and process the high-order quantized data to obtain the phase to be adjusted at the first sampling moment. Wherein, the first phase detector in the first clock data recovery unit uses the characteristic of the sampling value h(0)=h(1) of the impulse response function of the channel when the phases of the clock and data are synchronized as the phase detection standard.

[0034] In a specific implementation, the above-mentioned first clock data recovery unit may directly collect high-bit quantized data output by the ADC, or may collect high-bit quantized data after serial-to-parallel conversion of the ADC. The serial-to-parallel conversion refers to converting one channel of serial data...

Embodiment 2

[0053] This embodiment provides a serial receiver, including the clock data recovery circuit described in Embodiment 1.

[0054] In an optional implementation manner, the serial receiver further includes an analog front-end, a serial-to-parallel conversion unit, a digital calibration unit, and an equalizer connected in sequence. The analog front-end includes an ADC, which is used to receive and sample the analog signal transmitted by the serial transmitter through the channel.

[0055] In specific implementation, such as Figure 5 As shown, the above-mentioned analog front-end also includes CTLE (Continuous Time Linear Equalization, continuous time linear equalizer) 101, the ADC can be a time-interleaved ADC102, which is formed by time interleaving of 32 sub-channel ADCs of 1GS / s, and the output data is converted through serial and parallel The 1:4 serial-to-parallel conversion of the unit enters the digital domain, and is completed at a rate of 250MHz in the digital calibrat...

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Abstract

The invention discloses a clock data recovery circuit and a serial receiver. The clock data recovery circuit comprises a first clock data recovery unit, a second clock data recovery unit and a phase interpolator. The first clock data recovery unit is used for collecting high-order quantized data of the ADC and processing the high-order quantized data to obtain a first sampling moment phase to be adjusted; the second clock data recovery unit is used for collecting data, subjected to digital calibration and equalization processing, of the ADC and processing the data to obtain a to-be-adjusted second sampling moment phase; the phase interpolator is used for updating the sampling clock phase of the ADC according to the fluctuation amplitude of the phase at the first sampling moment and the phase at the second sampling moment, and the iteration result of the first clock data recovery unit and the iteration result of the second clock data recovery unit are fused, so that the loop delay of the clock data recovery circuit is reduced; and meanwhile, the stability of the clock data recovery circuit is ensured.

Description

technical field [0001] The invention relates to the technical field of circuits, in particular to a clock data recovery circuit and a serial receiver. Background technique [0002] The serial communication chip is an indispensable module in high-speed wired data communication, which realizes high-speed data transmission with a small number of ports. At present, ultra-high-speed wired serial receivers with a rate above 56Gb / s generally adopt PAM4 (4Pulse Amplitude Modulation, the fourth-generation pulse amplitude modulation) modulation mode, and introduce ADC (Analog-to-Digital Converter, analog-to-digital converter) for analog The front-end signal is quantified. The equalization method adopts the combination of Feed-forward Equalization (FFE) and Decision-feedback Equalization (DFE), and achieves better high-order equalization through feed-forward equalization technology, which improves the efficiency of PAM4 modulation. Bit error rate of the whole system. [0003] At pre...

Claims

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Application Information

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IPC IPC(8): H04L7/00H04L7/033
CPCH04L7/0079H04L7/033
Inventor 舒芋钧
Owner 高澈科技(上海)有限公司