Double ferroelectric gate transistor based on two-dimensional semiconductor channel

Abstract

The invention discloses a double-ferroelectric-gate transistor based on a two-dimensional semiconductor channel. The defect of a traditional ferroelectric field effect two-dimensional transistor in the in-memory calculation aspect is overcome. Comprising a top gate electrode layer, a top ferroelectric layer, a two-dimensional semiconductor channel layer, a bottom ferroelectric layer and a bottom gate electrode layer which are vertically distributed on a substrate from top to bottom in sequence; the source electrode and the drain electrode are located on the two sides of the top ferroelectric layer respectively. The bottom gate electrode layer, the drain electrode layer, the source electrode layer and the top gate electrode layer are made of metal Au materials, the two-dimensional semiconductor channel layer is made of MoS2 or MoTe2 materials, and the bottom ferroelectric layer and the top ferroelectric layer are made of P (VDF-TrFE) materials. According to the invention, the TMDC channel is electrically regulated and controlled through the coupling effect of the double ferroelectric gates, and the non-volatile conductivity of the TMDC channel is adjusted. Meanwhile, the double-ferroelectric-grid two-dimensional transistor adopts independent polarization of an upper ferroelectric layer and a lower ferroelectric layer as two logic inputs, double-input Boolean storage logic operation and non-volatile maintenance of a logic state of the double-input Boolean storage logic operation can be achieved according to four different combinations of polarization directions in the double ferroelectric grids, and therefore the function of in-memory calculation is achieved.

Description

technical field [0001] The invention belongs to the technical field of microelectronic devices, and in particular relates to a double ferroelectric gate two-dimensional transistor that can use a single transistor structure to realize in-memory computing, which helps to promote the next generation of in-memory computing devices with high energy efficiency ratio and high area efficiency development of. Background technique [0002] With the emergence of emerging smart applications such as artificial intelligence Internet of Things (AIoT), robotics, and edge computing, the information processing system of smart devices needs to process massive unstructured data in real time and efficiently. However, due to the bottleneck of the "memory wall" of the traditional von Neumann architecture, the traditional information processing system has been difficult to meet the data-intensive computing needs of current smart devices. In-memory computing is a technical solution proposed to solv...

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Problems solved by technology

However, limited by its single-gate structure, ferroelectric field-effect two-dimensional transistors that can realize single-transistor Boolean logic gates have not been reported yet.

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