Clock signal dynamic alignment method and phase aligner

Abstract

The invention discloses a clock dynamic alignment method and a phase aligner. The method comprises the following steps: generating a plurality of derived clocks with discrete phases according to an original clock; performing iterative adjustment on the output clock until the rising edge of the output clock is between the rising edge of the original clock and the rising edge of the first derived clock; the first derived clock is the derived clock with the minimum phase deviation value with the original clock; and during each iterative adjustment, comparing the rising edge of the output clock with the original clock and the first derived clock, updating a count value according to the comparison result, selecting a derived clock from the derived clocks as a selected derived clock according to the updated count value, inputting the selected derived clock to the programmable logic block array, and outputting the selected derived clock to the programmable logic block array. And then the adjusted output clock is obtained from the tail end of the programmable logic block array. According to the invention, dynamic compensation can be carried out according to the temperature or voltage change of the FPGA, and the phase alignment effect of the output clock and the original clock is improved.

Description

technical field [0001] The invention relates to the technical field of digital chip design, in particular to a clock dynamic alignment method and a phase aligner. Background technique [0002] FPGA is a programmable device. There are programmable logic block arrays that can be programmed by users in FPGA, as well as customized hard cores. Sometimes the clock generated by the hard core needs to be used by the programmable logic block array. At this time, the original clock signal given by the hard core is generally routed to the global / local clock driver first, and then drives the Fabric through the global / local clock network (structure , refers to the user program in the programmable logic block array), but the original clock signal will be delayed in the programmable logic block array, but usually, due to the delay of the global / local clock driver and the programmable logic block array, When the original clock signal reaches the end of the programmable logic block array, ...

AI Technical Summary

Problems solved by technology

Sometimes the clock generated by the hard core needs to be used by the programmable logic block array. At this time, the original clock signal given by the hard core is generally routed to the global / local clock driver first, and then drives the Fabric through the global / local clock network (structure , refers to the user program in the programmable logic block array), but the original clock signal will be delayed in the programmable logic block array, but usually, due to the delay of the global / local clock driver and the programmable logic block array, When the original clock signal reaches the end of the programmable logic block array, its phase has a large deviation from the phase given by the hard core. In order to solve this problem, the prior art adopts PLL (phase-locked loop) to realize phase alignment (in In actual operation, the rising edge of the output signal at the end of the programming logic block array is generally adjusted to the position adjacent to the rising edge of the original clock signal to achieve macroscopic phase alignment), but the PLL uses a method of fixedly moving the phase, by setting in advance The phase shift amplitude realizes fixed phase shift compensation, and the delay of the original clock signal in the programmable logic block array will change with the temperature or voltage of the FPGA, and the existing PLL cannot be dynamically compensated according to the temperature or voltage change of the FPGA , the phase alignment effect is poor

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