superjunction semiconductor device

Abstract

The present invention relates to a superjunction semiconductor device. In at least one cell structure of the superjunction semiconductor device, the first-type body region includes at least two segmented body regions arranged in the third direction, and the source region is disposed in a part of the segmented body region away from the drain region The surface of the gate oxide layer is arranged on the surface of another part of the segmented body region away from the drain region, and the gate is arranged on the surface of the gate oxide layer away from the segmented body region. In this cell structure, The segmented body region where the gate oxide layer and the gate are arranged is separated from the segmented body region where the source region is arranged, which can weaken the shielding effect of the first type doping column on the gate, and can increase the Miller capacitance Cgd compared with the traditional structure. Helps reduce turn-off speed, reduce overshoot voltage, improve EMI problems, and studies have shown that it has less impact on Qg and device withstand voltage performance.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and in particular, to a superjunction semiconductor device. Background technique [0002] In the superjunction semiconductor device, a longitudinally extending P-type doped column is inserted into the drift region of a traditional power device. In the off state, the PN junction formed by the P-type doped column and the adjacent N-type doped column depletes each other, forming a 3D -RESURF (Reduced Surface Electric Field) effect, a smaller on-resistance Ron can be obtained while meeting the withstand voltage of the device. [0003] like figure 1 and figure 2 As shown, in a cell structure of a superjunction semiconductor device, a P-type body region 20 (P body) is provided on the top of a P-type doping column 11 provided in the drift region 10, and a P-type body region 20 is provided on the top surface of the P-type body region 20 for The N+ source region 20a in contact with the ...

AI Technical Summary

Problems solved by technology

In this cellular structure, since the vertically extending P-type doped columns 11 form a shielding effect on the polysilicon gate 14, the Miller capacitance Cgd is relatively low, which easily leads to an excessively fast turn-off speed and a large overshoot voltage, which may can cause serious EMI problems

[0004] Appropriately increasing the Miller capacitance Cgd can reduce the turn-off speed and reduce the overshoot voltage, but blindly increasing the Miller capacitance Cgd will also cause an increase in Qg (gate charge), resulting in greater switching loss, and may also affect the device endurance. Therefore, the preferred way is to increase the Miller capacitance Cgd to reduce the turn-off speed and reduce the overshoot voltage, while avoiding affecting Qg and device withstand voltage performance

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