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Single event effect test method and device for SerDes module of FPGA device

A single event effect and test method technology, applied in the field of integrated circuits, can solve the problems of poor test applicability, low accuracy, and low stability, and achieve the effects of reducing interference, improving effectiveness, and reducing errors

Pending Publication Date: 2022-05-24
FUDAN UNIV
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  • Application Information

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Problems solved by technology

[0005] This application provides a single event effect test method, device, electronic equipment and storage medium for the FPGA device SerDes module to solve the low stability, low accuracy and poor real-time performance of the FPGA device SerDes module test in the related art , and problems such as poor test applicability

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  • Single event effect test method and device for SerDes module of FPGA device
  • Single event effect test method and device for SerDes module of FPGA device
  • Single event effect test method and device for SerDes module of FPGA device

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Embodiment Construction

[0034] The following describes in detail the embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, and are intended to be used to explain the present application, but should not be construed as a limitation to the present application.

[0035] In the related art, it is difficult for the testing technology to accurately locate the position of the SerDes to be tested on the FPGA, which will inevitably cause other resources to be affected by radiation and cause single event effects, reducing the accuracy of the test data. The embodiment of the present application adopts the method of bit stream analysis, by modifying the test link, comparing the difference of the underlying bit stream information co...

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Abstract

The invention relates to the technical field of integrated circuits, in particular to a single event effect test method and device for a SerDes module of an FPGA device, and the method comprises the steps: generating a first SBS code of a target code type through a first FPGA device as a main control device; in the process of transmitting the first SBS code by a second FPGA device serving as the to-be-tested equipment, controlling the first FPGA device to enable the first SBS code to receive radiation, and detecting a second SBS code of a target code type after radiation; and counting the error code number and the error type of the SBS according to the second SBS code, and generating a single event effect test result. Therefore, the problems of low stability, low accuracy, poorer real-time performance, poorer test applicability and the like of the SerDes module test of the FPGA device in related technologies are solved.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, and in particular, to a single event effect test method for a SerDes (Serializer / De-serializer, serializer / deserializer) module of an FPGA (Field Programmable Gate Array) device and the device. Background technique [0002] The SRAM (Static Random Access Memory, Static Random Access Memory) type FPGA with the advantages of reconfigurability and high integration has strongly supported the development of my country's aviation and aerospace technology. Most of SRAM-type FPGAs integrate SerDes to meet the demand for higher transmission rates for mass data transmission. However, SRAM-type FPGAs are very sensitive to Single Event Effect (SEE), and in harsh radiation environments, SEU (Single Event Upset, Single Event Upset) and SEFI (Single Event Functional Interrupt) can easily occur in the internal SerDes. particle function interruption), resulting in data errors and immeasura...

Claims

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Application Information

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IPC IPC(8): G01R31/28G01R31/317G01R31/3181G06F17/13
CPCG01R31/2851G01R31/2872G01R31/2881G01R31/31702G01R31/3181G06F17/13
Inventor 吴泽昊蔡畅沈磊俞军王树徐灵炎宁冰旭沈鸣杰徐烈伟
Owner FUDAN UNIV
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