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Bus bridge, system and method from AHB bus to I2C bus

A bus bridge and bus technology, applied in the bus field, can solve problems such as unfavorable IP multiplexing, AHB bus occupation, and difficulty in I2C device integration, and achieve the effects of improving security, reducing burden, and high compatibility

Active Publication Date: 2022-05-31
四川创安微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Such modification is not conducive to the reuse of IP
[0004] In addition, different I2C slave devices will design different I2C transmission formats according to their own characteristics, which causes great difficulties when these I2C devices are integrated into the same system
[0005] The AHB bus is used for high performance and high clock frequency system modules, while the I2C bus is used for low clock frequency system modules. Simple protocol conversion will cause the AHB bus to be occupied for a long time

Method used

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  • Bus bridge, system and method from AHB bus to I2C bus
  • Bus bridge, system and method from AHB bus to I2C bus
  • Bus bridge, system and method from AHB bus to I2C bus

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Embodiment 1

[0084] Such as Figure 1 to Figure 8 Shown, the bus bridge of a kind of AHB bus of the present invention to I2C bus, AHB bus protocol is mapped into I2C bus protocol by this bus bridge; Described bus bridge is as the master of I2C bus, simultaneously as a slave of AHB advanced system bus ;Receive the transmission command from the AHB master through the AHB bus, analyze the transmission command, convert it into a transmission command conforming to the I2C protocol, and issue the I2C transmission command through the I2C bus to communicate with the I2C slave. For the write transfer command, the bus bridge sends the data to the corresponding I2C slave through the I2C bus after receiving the target address, transfer data and necessary control information from the AHB master. For the read transfer command, after receiving the target address and necessary control information from the AHB master, the bus bridge reads data from the corresponding I2C slave through the I2C bus and caches...

Embodiment 2

[0180] Such as Figure 1 to Figure 8 As shown, the difference between this embodiment and Embodiment 1 is that this embodiment provides a bus bridge system from an AHB bus to an I2C bus, and the bus bridge system includes an AHB host, an AHB bus, a bus bridge, an I2C bus and several I2C slave, the AHB master is connected to the bus bridge through the AHB bus communication, and the bus bridge is connected to several I2C slaves through the I2C bus communication;

[0181] Wherein, the bus bridge adopts the bus bridge from the AHB bus to the I2C bus described in Embodiment 1.

Embodiment 3

[0183] Such as Figure 9 , Figure 10 As shown, the difference between this embodiment and Embodiment 1 is that this embodiment provides a bus bridge control method from the AHB bus to the I2C bus, and the control method is applied to the AHB bus to the I2C bus described in Embodiment 1. The bus bridge, the control method includes:

[0184] Step A, obtain the data forwarding request of the AHB master to the internal register of the I2C slave, and wait for the completion of the AHB master setting;

[0185] Step B, enable the data transmission start signal, take out the slave address from the CR0 register, and splice the transmission direction W at the end to form a byte of data (that is, the slave address 7bit + write 1bit), and send it to the I2C host through the write data channel module;

[0186] Step C, wait for the data forwarding request of the I2C master module, if there is a data forwarding request, take out the internal register address of the I2C slave from the CR4...

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PUM

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Abstract

The invention discloses a bus bridge, system and method from an AHB bus to an I2C bus. The bus bridge comprises an AHB slave module, a register module, a data caching module, a security configuration module, a transmission control module, an I2C host module, an anomaly detection module and an interrupt control module. And mapping the AHB bus protocol into an I2C bus protocol through a bus bridge. The bus bridge system comprises an AHB host, an AHB bus, a bus bridge, an I2C bus and a plurality of I2C slaves, the AHB host is in communication connection with the bus bridge through the AHB bus, and the bus bridge is in communication connection with the I2C slaves through the I2C bus. According to the invention, on the basis of SoC chips which need to use various multiplexing IPs, transmission communication of a cross-bus protocol is processed through the bus bridge provided by the invention; the transition from the rapid transmission rate of the AHB to the low transmission rate of the I2C is realized; according to the invention, the address width configuration function of the register in the I2C slave is realized.

Description

technical field [0001] The invention relates to the field of bus technology, in particular to a bus bridge, system and method from an AHB bus to an I2C bus. Background technique [0002] With the maturity of deep submicron process technology, the scale of integrated circuit chips is getting larger and larger. Digital IC has developed from a timing-driven design method to a design method based on IP (Intellectual Property) multiplexing, and has been widely used in System-on-chip (SoC) design. In SoC design based on IP multiplexing, on-chip bus design is the most critical issue. For this reason, many on-chip bus standards have emerged in the industry. Among them, the AMBA on-chip bus launched by ARM has been favored by the majority of IP developers and SoC system integrators, and has become a popular industry-standard on-chip structure. The AMBA specification mainly includes the AHB system bus and the APB system bus. SoC chips in the fields of industrial control, consumer e...

Claims

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Application Information

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IPC IPC(8): G06F13/38G06F13/40G06F13/42G06F15/78
CPCG06F13/385G06F13/4027G06F13/4282G06F15/7807G06F2213/0016Y02D10/00
Inventor 不公告发明人
Owner 四川创安微电子有限公司