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Semiconductor packaging method

A packaging method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems affecting packaging efficiency and time-consuming grinding process, so as to save grinding time, improve packaging efficiency, and improve quality Effect

Pending Publication Date: 2022-06-03
SIPLP MICROELECTRONICS CHONGQING CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the grinding process is time-consuming, which affects the packaging efficiency

Method used

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  • Semiconductor packaging method
  • Semiconductor packaging method
  • Semiconductor packaging method

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Embodiment Construction

[0041] Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. Where the following description refers to the drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as recited in the appended claims.

[0042] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this application and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and / or" as use...

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Abstract

The invention provides a semiconductor packaging method. The semiconductor packaging method comprises the steps that a packaging structure is formed, the packaging structure comprises a packaging layer and at least one chip, the packaging layer is provided with at least one concave cavity, the at least one chip is arranged in the at least one concave cavity, the front face of the chip is exposed out of the packaging layer, and the packaging layer is arranged on the packaging layer; a plurality of welding pads are arranged on the front surface of the chip; forming a rewiring structure on the packaging structure, wherein the rewiring structure leads out a welding pad of the chip; and sleeving the rewiring structure with an insulating film layer provided with a hollow part, wherein the surface, deviating from the chip, of the rewiring structure exposes the insulating film layer through the hollow part.

Description

technical field [0001] The present application relates to the field of semiconductor technology, and in particular, to a semiconductor packaging method. Background technique [0002] Common semiconductor packaging technology, such as chip packaging technology, mainly includes the following process: For the front side of the chip, the front side of the chip is firstly mounted on the carrier board, followed by thermocompression molding, peeling off the carrier board, and then A redistribution structure is formed on the front side of the chip, then an insulating layer for protecting the redistribution structure is formed on the redistribution structure, and the surface of the redistribution structure facing away from the chip exposes the insulating layer. [0003] In the existing chip packaging technology, when an insulating layer is formed on the rewiring structure, the initially formed insulating layer completely covers the rewiring structure, and then the insulating layer is...

Claims

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Application Information

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IPC IPC(8): H01L21/56
CPCH01L21/561H01L21/568
Inventor 涂旭峰霍炎
Owner SIPLP MICROELECTRONICS CHONGQING CO LTD