Main frequency evaluation method for hardware simulation platform

Abstract

The invention discloses a dominant frequency evaluation method for a hardware simulation platform. The dominant frequency evaluation method comprises the following steps: acquiring partition information and hardware simulation platform information; the partitions are placed on the corresponding FPGAs, and signals between the partitions are transmitted through physical connection lines between the corresponding FPGAs; obtaining the number of transmitted signals and the number of physical connection lines, judging whether the number of the transmitted signals is greater than the number of the physical connection lines, and if yes, performing TDM distribution on the intra-group signals between the partitions; and calculating the TDM ratio of each port pair between the FPGAs, calculating the time delay between the port pairs in the FPGA pairs according to the TDM ratio of each port pair, the parameters of the FPGA platform and the preset beat number of signal arrival, taking the maximum value of the time delay as the time delay of the evaluation, and obtaining a main frequency evaluation result in combination with a preset time delay-main frequency corresponding relationship. Developers can conveniently optimize division and mapping strategies.

Description

Technical field [0001] The present invention belongs to the field of integrated circuit microelectronics, in particular relates to a main frequency evaluation method for hardware simulation platforms. Background [0002] Due to the shrinking size of transistors and the improvement of the design process, the computing power of modern digital systems has greatly improved over the past few years. But this increases the complexity of the design, resulting in an increasing cost of validating chips. If the final product is not designed to meet the requirements, the upfront investment will be lost, so chip verification becomes very important. [0003] Compared with the simulation with an emulator or accelerator, the FPGA is closer to the real chip and can cooperate with the developer to develop the underlying software. However, due to the huge area, performance and power gap between FPGAs and asematic circuits (ASICs). Therefore, a complex SoC design cannot be prototyped on a single FPG...

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Problems solved by technology

[0004] However, the division of VLSI circuits cannot directly determine the final simulation rate. It is also necessary to place the divided blocks on the corresponding FPGA and perform TDM distribution on the cutting signals to determine the final performance.

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