Semiconductor structure and manufacturing method thereof

Abstract

The semiconductor structure includes a first finfet cell and a second finfet cell. Each of the first finfet cells has an analog fin boundary according to an analog circuit design rule, and each of the second finfet cells has a digital fin boundary according to a digital circuit design rule. The semiconductor structure further includes a first circuit formed with first finfet cells, a second circuit formed with second finfet cells, and a third circuit formed with one or more of the first finfet cells and one or more of the second finfet cells. The embodiment of the invention also relates to a method for manufacturing the semiconductor structure.

Description

technical field [0001] Embodiments of the present application provide semiconductor structures and methods of fabricating the same. Background technique [0002] Electronic circuits continue to be designed and manufactured to operate at higher and higher operating speeds. Circuits such as serializer / deserializer (serdes) circuits currently operate in the frequency range from 28 gigabits per second (Gbps) to 448 Gbps. In the past, these circuits have been designed using analog circuit design rules that include analog fin formation or boundaries. Key device parameters for operation at these speeds include transconductance (GM), unity gain frequency (UGF), and electromigration (EM) current. To achieve higher operating speeds, all three key device parameters have used larger contact polysilicon (poly) pitch (CPP), wider metal over diffusion [source / drain contacts] (MD), more Larger vias, wider metal lines and larger spacing to increase. Changing these structures can reduce r...

AI Technical Summary

Problems solved by technology

However, as design and manufacturing processes are scaled down, performance improvements using analog circuit design rules and analog fin boundaries are limited by device size

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