Power management circuit, system-on-chip device, and power management method

Abstract

The invention provides a power management circuit, system-on-chip equipment and a power management method. A circuit includes a power detector and a logic circuit. The power detector is configured to output a first power management signal according to a state signal and a first power supply signal from a first power supply. The circuit is configured to operate in different modes in response to a status signal. The logic circuit is configured to output a second power management signal according to the first power management signal and the status signal.

Description

technical field [0001] The present application relates to the field of circuits, and more particularly to a power management circuit, a system-on-chip device, and a power management method. Background technique [0002] Dual-rail devices, such as dual-rail static random access memory (SRAM), have different logic circuits that operate at different supply voltages. For example, one part of the SRAM (called memory peripheral logic) can operate at a lower supply voltage than some memory arrays, another part of the SRAM (they operate at a higher supply voltage) to reduce dynamic power consumption. This technique allows the required active power to be reduced while maintaining adequate performance. However, dual-rail designs suffer from severe cross-domain leakage when both supplies are turned on or off. SUMMARY OF THE INVENTION [0003] According to a first aspect of embodiments of the present application, there is provided a circuit comprising: a power detector configured to...

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Problems solved by technology

However, the dual-rail design suffers from severe cross-domain leakage when the two supplies are switched on or off

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