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Novel construction method for integrated circuit layout data index

A technology of layout data and integrated circuits, applied in database indexing, database updating, structured data retrieval, etc., can solve the problems of high construction cost of RTree or R*Tree, low space utilization of quadtree or RTree, overlapping of RTree pages, etc. problem, to achieve the effect of stable query efficiency, reduced construction time complexity, and improved construction speed

Pending Publication Date: 2022-07-12
SUN YAT SEN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Quadtrees represent the division of two-dimensional space by decomposing the area into four equal quadrants, sub-quadrants, etc., until the contents of the cells meet certain data occupancy criteria. The cell size of the grid varies with data density, while The setting of the cell size also directly affects the space utilization, too small a cell will lead to a huge space occupation
[0008] 1. Quadtree or R Tree space utilization is low
[0009] 2. There is a page overlap problem in R Tree
[0010] 3. The construction cost of R Tree or R*Tree is relatively high

Method used

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  • Novel construction method for integrated circuit layout data index
  • Novel construction method for integrated circuit layout data index
  • Novel construction method for integrated circuit layout data index

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Experimental program
Comparison scheme
Effect test

Embodiment

[0064] 1. Combine with figure 2 As shown, the steps of realizing the present invention are as follows:

[0065] (1) Read spatial data

[0066] First read the spatial data in the integrated circuit GDS file, then create a memory for the spatial data in the system stack space, and record the addresses of all the spatial data in the stack memory.

[0067] (2) Build an index

[0068] All spatial data is processed hierarchically according to the layer number. The spatial data of each layer is constructed by batch construction method to build a single-layer layer index database, and the link is completed through the multi-layer layer index database. When building a single-layer layer index database, the method of batch loading is used to build, and a total of four-level indexes of LL.x, LL.y, UR.x, and UR.y are constructed. The actual address of all spatial data in the stack space is stored in the In the value of the fourth-level index UR.y.

[0069] (3) Query operation

[007...

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Abstract

The invention discloses a novel construction method of an integrated circuit layout data index. The method comprises four-stage indexing, dynamic uniform partitioning and spatial data object represented by using a minimum bounding box. Wherein the four-level indexes comprise a first-level index with a keyword being a lower left corner coordinate X, a second-level index with a keyword being a lower left corner coordinate Y, a third-level index with a keyword being an upper right corner coordinate X and a fourth-level index with a keyword being an upper right corner coordinate Y. The indexing method is low in construction cost, low in space occupation and stable and rapid in query, and can be widely applied to the field of integrated circuit electronic design automation as an indexing method of the integrated circuit layout data.

Description

technical field [0001] The invention relates to the field of database indexing in computer-aided design, and is aimed at an integrated circuit EDA tool, in particular to a new construction method of integrated circuit layout data index, in particular. Background technique [0002] The layout of an integrated circuit mainly records the spatial data such as points, rectangles, and polygons of the layout. With the development of integrated circuit technology and the increase in the complexity of design, the feature size of the device is further reduced, and the layout scale of the integrated circuit becomes larger and larger. Whether it is an integrated circuit layout automation generation EDA (Electronic Design Automation) tool or a verification EDA tool, it is inevitable to face huge layout data processing problems. For example, the layout and routing process in the layout automation generation EDA tool requires high-speed extraction and routing layout process. Another examp...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F16/22G06F16/2458G06F16/27G06F16/23G06F30/392G06F30/394
CPCG06F16/2264G06F16/2474G06F16/278G06F16/23G06F30/392G06F30/394
Inventor 孟祥雨曾洵
Owner SUN YAT SEN UNIV