Conversion interface of standard communication protocol and on-chip packet transport protocol for interconnection of multiple bare cores

Abstract

The invention relates to a conversion interface for a multi-bare-core interconnected standard communication protocol and an on-chip packet transport protocol, the structure of the conversion interface is derived based on a mainstream NI structure, the conversion interface is mainly composed of a protocol controller and an event controller, the structure is clear and concise, the realizability is high, and all parts of the interface are mutually independent and low in dependency. And the protocol controller is composed of three parts, namely a Shell, a Buffer and a Kernel. The event controller is responsible for managing events passing through an interface and is composed of a sending buffer area, a receiving buffer area and an event queue. According to the unified interface structure oriented to the on-chip packet transmission protocol and the standard communication protocol, the problems of protocol conversion, data packet generation and analysis (packaging and unpackaging), cross-clock domain transmission of data and the like can be solved, and a reliable communication path and method are provided for an on-chip network and a bare chip.

Description

technical field [0001] The present invention relates to the communication technology of bare chip and on-chip packet transmission protocol, in particular to a conversion interface between a standard communication protocol interconnected with multiple bare chips and an on-chip packet transmission protocol. Background technique [0002] In a monolithic ASIC, all components are designed and fabricated on a single silicon wafer using the same process. As process dimensions shrink, the cost and development cycle to develop a monolithic ASIC becomes extremely high. In this case, multi-die integration is an inevitable choice for the development of high-performance chips in the future, that is, multiple chip components with different functions that have been verified and unpackaged are interconnected and assembled, and packaged as chips in the same package As a whole, a package-level network NoP (Network on Package) is formed, and an integrated microsystem is then constructed. The...

AI Technical Summary

Problems solved by technology

The large increase in the number of chips makes the traditional bus-type interconnection architecture unable to meet the high-speed communication tasks between the chips. In this case, the NoC (Network on Chip) came into being.

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