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Circuit and method for restoring digital clock signal

A technology for recovering circuits and digital clocks. It is used in signal processing, recording signal processing, and digital transmission systems using self-timed codes. It can solve problems such as difficult functions, analog structure implementation, and changing frequency band mixing.

Inactive Publication Date: 2004-11-24
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

These functions are difficult to realize by analog structure
[0009] Also, when the LPF 140 for supplying the frequency error and the phase error as the control voltage of the VCO 150 is realized by an analog circuit, it is impossible to change the frequency band freely and noise is mixed in the signal
Therefore, it is difficult to apply the LPF realized by the analog structure to a newly developed optical disc product corresponding to a high multiple speed mode.

Method used

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  • Circuit and method for restoring digital clock signal
  • Circuit and method for restoring digital clock signal
  • Circuit and method for restoring digital clock signal

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Embodiment Construction

[0025] figure 2 is a block diagram of an embodiment of a digital clock recovery circuit according to the present invention, in figure 2 Among them, an analog-to-digital (A / D) converter 210 converts an analog signal read from the optical disc 200 into digital data. The asymmetry corrector 220 generates a corrected binary level according to the statistical characteristics of the received signal, thereby binarizing the analog signal in an optimal state, and corrects the binary level of the digital data provided by the A / D converter 210 according to the corrected binary level. level, and the corrected digital data is supplied to the frequency error detector 230 and the phase error detector 240.

[0026] Frequency error detector 230 obtains the frequency difference between the received signal provided by asymmetry detector 220 and the system clock signal generated by VCO 270 and provides a frequency error signal.

[0027] When the system clock signal is substantially locked to ...

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Abstract

A circuit for recovering a digital clock signal and a method therefor is disclosed. The digital clock recovery circuit includes an analog-to-digital (A / D) converter and asymmetry corrector for converting a received analog signal into digital data and providing corrected digital data corrected by a binarization level which traces the center value of the received signal, a frequency error detector for detecting a frequency error from the corrected digital data, a phase error detector for detecting a phase error from the corrected digital data, and a digital low pass filter (LPF) for providing the frequency error and the phase error as a control voltage. It is possible to trace the asymmetry of the received signal more sensitively than in the conventional technology by realizing an asymmetry corrector for correcting the asymmetry of the digital data which has undergone the analog-to-digital (A / D) conversion, the phase error detector, and the LPF by a digital circuit, thus generating a system clock signal and to improve the reliability of the system by stably generating the system clock signal.

Description

technical field [0001] The present invention relates to the field of clock signal recovery, and in particular to a circuit and method for recovering a digital clock signal in a recording and / or playback device for an optical disc. Background technique [0002] In an apparatus for recording data on or reproducing data from an optical disc such as a compact disc (CD) or a digital versatile disc (DVD), a process for synchronizing a playback signal with a system clock signal is necessary. A phase-locked loop (PLL) circuit is one circuit used to perform this processing. [0003] The PLL circuit locks a phase by generating a system clock signal relative to a received signal through a voltage controlled oscillator (VCO) oscillating at a certain frequency, changing the frequency of the system clock signal, and locking the received signal to the changing system clock signal. Generally, after calculating the difference between the oscillation frequency of the VCO and the frequency of...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11B20/10G11B20/14H03L7/00H03L7/08H03L7/087H03L7/113H04L7/033
CPCG11B20/1403G11B20/10037H04L7/0334H04L7/033H03L7/0807H03L7/087G11B20/10203H04L7/0331H03L7/113
Inventor 朴贤洙沈载晟元容光
Owner SAMSUNG ELECTRONICS CO LTD