Negative voltage decoding circuit

Abstract

The negative voltage decoding circuit belongs to the technical field of mixed signal processing integrated circuit and non-volatile memory circuit design. It is characterized in that the first-stage negative voltage level conversion circuit includes: two inverters composed of PMOS transistors and NMOS transistors respectively, and the input terminals and output terminals of the two inverters are connected to each other to form positive feedback of the output voltage Channel, the output positive high voltage is transmitted by the PMOS tube of one of the inverters, and the negative low voltage is transmitted by the NMOS tube; a CMOS inverter working under the input voltage makes the branch currents on both sides asymmetrical; two inverters The initial input voltage is determined by two PMOS transistors whose gates are grounded. There is also a reading discharge path, so that the ground level output during normal reading is transmitted by the NMOS tube whose gate is connected to the positive high voltage, avoiding the loss transmitted by the PMOS tube. The invention has fast level conversion speed, increases the ability to reduce the size of the transistor, and has no loss of ground level transmission during normal reading.

Description

technical field [0001] The negative voltage decoding circuit relates to the technical fields of mixed signal processing integrated circuit and non-volatile memory circuit design. Background technique [0002] Currently, among non-volatile memories, flash memory (Flash Memory) is developing rapidly due to its high programming speed, high integration and superior performance. In 1984, Masuoka and others proposed the concept of flash memory for the first time, that is, the high speed of flash erasing was realized by erasing and programming by bit and bit by block (sector), and eliminated EEPROM (Erasable Programmable Read-only memory: Erasable Programmable Read-only memory: Erasable Programmable Read-only memory) necessary selector for programming read-only memory). [0003] figure 1 Represents the layout of a memory array. When the memory performs an erasing operation on a selected block, it is necessary to add a corresponding erasing voltage (generally a negative voltage) ...

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Problems solved by technology

A CMOS inverter is also used to make the power supply of the two branches asymmetric, so that the driving current required by the negative high-voltage level shifting circuit during conversion is greatly reduced, thereby overcoming the traditional negative high-voltage level shifting circuit due to the input voltage Defects caused by the circuit not working properly due to lower

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